This exam is 7 pages long and has 6 questions.
You must show all of your work -- partial credit may be given to partially correct answers, while answers with no justification may not receive full points. Use the back of the exam sheets if you need extra space.
1) (16pts) a) Name the programmer visible registers of the Pentium. Briefly explain the original (8086) purpose of BP, SI and ES.
b) How are the EFLAGS bits O, S, Z and C useful in a program? You do NOT have to define them or give an example of their use -- just explain (1 or 2 sentances) in the general sense.
c) Give the sequence of operations performed by an INT instruction.
d) The six segment registers on the Pentium each have a programmer invisible "cache" descriptor register associated with them. What is the purpose of this cache?
2) (18 pts) a) How are the Segment registers, CS and DS, interpreted in Real Mode?
How has this changed in Protected mode?
Label the fields of the protected mode CS register.
b) Explain the purpose of the Base, Limit and G fields in the segment descriptor shown:
c) The Segmentation system on the Pentium allows the operating system to partition a program abstractly into three sections. Name them, and identify and BRIEFLY explain the THREE fields in the following Access Rights byte that provide control over this abstraction. Do NOT worry about specific values, only the semantics.
3) (16 pts) a) The Paging system on the Pentium allows the operating system to abstract memory as a set of fixed sized blocks. What problem does this address in a multiprogrammed segmented computer system?
b) Using both segmentation and paging, the following address translation process is possible. Given the virtual address, compute the linear address.
c) What is the physical address of the next instruction?
d) How many memory accesses may occur in the worst case?
4) (20 pts) a) How many data addressing modes are available on the Pentium?
b) Name the address mode used in the instructions below and fill in the boxes with a register designator or memory address given the information at the top. Assume Real mode of operation.
c) How is the destination address computed for PC-relative control flow instructions?
d) Give an example of an unconditional jump instruction that is NOT PC-relative.
e) Briefly explain the advantages of using an the interrupt vector table as a mechanism for applications to make system calls and for hardware to request service.
5) (12 pts) The format of the first two bytes of a typical instruction is shown below along with a set of tables defining the fields.
a) Give the values of the first two bytes for the following instructions if operating in 16-bit instruction mode.
b) Give the instruction encoded by the following if operating in 32-bit mode:
6) (18 pts) a) The following two instructions perform the same operation.
Which one is faster (a) or (b)? If (b) is faster, what is the purpose of having an instruction of type (a)?
b) Briefly explain the operation performed by the instruction REP STOSW and any side effects.
c) Briefly explain how XCHG and XLAT differ.
d) Give an example of a C programming language construct for which CMOVZ AX, BX can be used as a translation.
e) Where is the result of IMUL BX stored?
f) What instruction(s) can be used to perform a 1's complement bit operation?