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We discussed IN, OUT, INS and OUTS as instructions for the transfer of data to and from an I/O device.
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IN and OUT transfer data between an I/O device and the microprocessor's accumulator (AL, AX or EAX).
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The I/O address is stored in:
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Register DX as a 16-bit I/O address (variable addressing).
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The byte, p8, immediately following the opcode (fixed address).
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Only 16-bits (A0 to A15) are decoded.
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Address connections above A15 are undefined for I/O instructions.
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0000H-03XXH are used for the ISA bus.
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INS and OUTS transfer to I/O devices using ES:DI and DS:SI, respectively.
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Isolated and Memory-Mapped I/O:
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In the Isolated scheme, IN, OUT, INS and OUTS are required.
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In the Memory-mapped scheme, any instruction that references memory can be used.
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8-bit port addresses used to access system board device, e.g. timer and keyboard.
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16-bit port addresses used to access serial and parallel ports, harddrives, etc.
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The basic input device (to the microprocessor) is a set of tri-state buffers.
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The basic output device (from the microprocessor) is a set of latches.
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In this case, the data from the OUT instruction is latched using SEL.
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I/O devices are typically slower than the microprocessor.
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Handshaking is used to synchronize I/O with the microprocessor.
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A device indicates that it is ready for a command or data (through some I/O pin or port).
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The processor issues a command to the device, and the device indicates it is busy (not ready).
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The I/O device finishes its task and indicates a ready condition, and the cycle continues.
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There are two basic mechanisms for the processor to service a device.
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Polling: Processor initiated. Device indicates it is ready by setting some status bit and the processor periodically checks it.
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Interrupts: Device initiated. The act of setting a status bit causes an interrupt, and the processor calls an ISR to service the device.
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A printer connected to the parallel port requires handshaking.
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The parallel port specification is shown below:
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The processor writes ASCII data out to the Datax pins of the printer and toggles the Data Strobe pin to latch it in.
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The printer raises the Busy pin.
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When the Busy pin goes low, the sequence repeats.
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The terminal characteristics of the processor must be matched to those of the I/O devices.
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Input Devices:
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TTL (0.0V-0.8V low and 2.0-5.0V high) or compatible.
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Switch-based; usually either open or connected.
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These must be conditioned before they can be used properly.
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For example, to make a simple (single-pole, single-throw) toggle switch TTL compatible:
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Input Devices:
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Mechanical switches physically bounce when they are closed (causing them to momentarily open after being closed).
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This can cause a problem if they are used as a clocking signal.
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Two asynchronous flip-flop solutions are given below:
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The basic idea is that these flip-flops store the values even if the D/D nodes both float.
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Output Devices:
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Interfacing an output device requires matching the voltage and current relationships of the devices and processor.
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Remember that the standard output levels of TTL compatible devices are 0.0 to 0.4V for logic 0 and 2.4V to 5.0V for logic 1.
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The current levels are 0.0 to 2.0mA (logic 0) and 0.0 to -400uA (logic 1).
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For memory-mapped I/O, decoding is identical to memory decoding.
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For isolated I/O, IORC and IOWC are developed using M/IO and W/R pins of the microprocessor.
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The text gives examples of 8-bit decoding and 16-bit decoding, which is a straightforward application of devices we've used for memory decoding.
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The I/O banks on the 8086 through the 80386SX are also set up like the memory.
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Similar to memory writes, any 8-bit I/O write request requires separate write strobes (BHE and BLE) but read requests do not.
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Output devices can be 16-bit in which case BHE is not needed.
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Input devices can be 8-bit or 16-bit.
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Note that instead of latches, high impedance buffers (74ALS244) are used in these cases.
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32-bit ports are becoming more popular because of PCI bus primarily.
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The EISA and VESA local bus are also 32-bit buses.
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For the 64-bit data buses of the Pentium, the I/O ports can appear in any of the 8 banks.
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However, only 32-bit transfers are supported, as there are no 64-bit transfer instructions.
