Intel Assembly

• Procedures:
• CALL: Pushes the address of the instruction following the CALL instruction onto the stack.
• RET: Pops the address.

• NEAR CALL:
• Similar to NEAR jump instruction, e.g. 2nd and 3rd bytes of instruction contain displacement added to IP.
• FAR CALL:
• Similar to FAR jump instruction, e.g. 2nd and 3rd bytes of instruction contain new IP while 4th and 5th bytes contain CS.
• CALL BX and CALL [BX] versions also exist.

Intel Assembly

• Interrupts:
• Hardware generated CALL: I/O Device
• Software generated CALL: Internally derived from an instruction or exception.
• We will look at both of these.

 

• Interrupt Vectors:
• Real Mode: A 4 byte number stored in the first 1024 bytes of memory.
• Protected Mode: A interrupt descriptor table is used instead.
• Each descriptor is 8 bytes long.

 

• There are 256 interrupt vectors.
• Intel reserves the 0-31.
• Interrupts 33-255 are user definable.

 

• Vectors 1-6, 7, 9, 16 and 17 function in real and protected mode.
• The rest function only in protected mode.

Intel Assembly

• Interrupt Vectors:

Number	Address	Microprocessor	Function
0	00-03	All	Divide error
1	04-07	All	Single step
2	08-0B	All	NMI pin
3	0C-0F	All	Breakpoint
4	10-13	All	Interrupt on overflow
5	14-17	80186-Pentium	Bound instruction (print screen)
6	18-1B	80186-Pentium	Invalid opcode
7	1C-1F	80186-Pentium	Coprocessor emulation
8	20-23	80386-Pentium	Double fault (clock tick)
9	24-27	80386	Coprocessor segment overrun (keyboard)
A	28-2B	80386-Pentium	Invalid task state segment (IRQ2)
B	2C-2F	80386-Pentium	Segment not present (IRQ3)
C	30-33	80386-Pentium	Stack fault (IRQ4)
D	34-37	80386-Pentium	General protection fault (IRQ5)
E	38-3B	80386-Pentium	Page fault (IRQ6)
F	3C-3F	-----	Reserved (IRQ7)
10	40-43	80286-Pentium	Floating-point error (Video)
11	44-47	80486SX	Alignment check interrupt
12	48-4F	Pentium	Machine check exception
13-1F	50-7F	---	Reserved

Intel Assembly

• Interrupt Instructions.
• Real mode: Fetches a vector from the vector table (address of ISR).
• Protected mode: Fetches an interrupt descriptor (contains addr of ISR).

 

• Similar to a FAR CALL: pushes both IP/EIP and CS onto stack.

 

• 3 types are available:
• INT
• There are 256 software interrupt instructions.
• The INT instruction takes a numeric operand: 0-255.

 

• Real mode: It's multiplied by 4 to get address of vector.
• Protected mode: It's multiplied by 8 (descriptors are 8 bytes long).

Intel Assembly

• INT Instruction.
• Processing sequence for an INT instruction:
• Push FLAGS.
• Clear T and I flag bits (hardware interrupts disabled).
• Push CS.
• Fetch new value for CS from interrupt vector.
• Push IP/EIP.
• Fetches new value of IP/EIP from vector.
• Jump to new location.

 

• INT instruction is 2 bytes long.
• Replaces FAR CALL, which is 5 bytes long.
• Commonly used to call system functions. Decouples programs from system function addresses.

 

• IRET(Real)/IRETD(Protected):
• Undoes call: POP IP/EIP, POP CS, POP FLAGS
• Popping FLAGS restores T and I bits.

Intel Assembly

• Interrupt Instructions.
• 2nd type:
• INTO
• Interrupt on overflow.
• Conditional software interrupt that tests the overflow flag (O).
• If O=0, INTO does nothing.
• If O=1, the procedure at interrupt vector 4 is called.

 

• 3rd type:
• INT3
• Designed to function like a breakpoint to debug software.
• It is a 1 byte instruction.

 

• Form of an ISR:

Intel Assembly

• Hardware Interrupt Control.
• STI: Places a 1 into the I flag, this enables interrupts.
• CLI: Places a 0 there, disabling interrupts.

 

• Miscellaneous Machine Instructions:
• STC (set carry), CLC (clear carry) and CMC (complement carry)
• In addition to propagating carry and borrow in multiple-word/double-word addition, these are used to return error conditions in system calls.
• C = 1: Error occurred.
• C = 0: No error occurred.

 

• HLT
• Stops instruction execution.
• Three ways to resume execution: interrupt, hardware reset or DMA operation.
• Used to synchronize hardware interrupts with system software.

Intel Assembly

• Miscellaneous Machine Instructions.
• LOCK Prefix:
• Appended to an instruction.
• Toggle the LOCK pin, disabling external bus masters and other peripherials.

 

• ENTER/LEAVE
• Used with stack frames, which provide a mechanism to pass stack parameters and allocate storage for local variables for procedures.
• ENTER pushes BP, and loads BP with the uppermost address of stack frame.
• Stack variables can then be accessed through the BP register.

 

• LEAVE restores previous values of BP and SP, e.g.
• MOV SP BP
• POP BP

Intel Assembly

• ENTER/LEAVE:

Intel Assembly

• ENTER/LEAVE: