-- UART BAUD RATE GENERATOR

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- N is the size of the register that holds the counter in bits.
-- M represents the modulo value, i.e., if 10, counter counts to 9 and wraps
entity BaudGen is
   generic(
      N: integer := 4;
      M: integer := 10
   );
   port(
      clk, reset: in std_logic;
      baud_tick: out std_logic;
      count_out: out std_logic_vector(N-1 downto 0)
   );
end BaudGen;

architecture beh of BaudGen is
   signal r_reg: unsigned(N-1 downto 0);
   signal r_next: unsigned(N-1 downto 0);
   begin

-- sequential logic that creates the FF
   process(clk, reset)
      begin
         if (reset = '1') then
            r_reg <= (others => '0');
         elsif (clk'event and clk='1') then
            r_reg <= r_next;
         end if;
   end process;

-- next state logic for the FF, count from 0 to M-1 and wrap
   r_next <= (others => '0') when r_reg=(M-1) else r_reg + 1;

-- output logic, output the actually count in the register, in case it's needed
   count_out <= std_logic_vector(r_reg);

-- generate a 1 clock cycle wide 'tick' when counter reaches max value
   baud_tick <= '1' when r_reg=(M-1) else '0';

end beh;