`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   13:40:26 10/04/2007
// Design Name:   transparport
// Module Name:   C:/jimp/CMPE415/415project_xilinx/datatranparport/transparport_tb.v
// Project Name:  datatranparport
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: transparport
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module transparport_tb_v;

// Inputs
   reg clk;
   reg reset;
   reg dvTf;
   reg dTf;

   // Outputs
   wire dvFf;
   wire dFf;

// Instantiate the Unit Under Test (UUT)
   transparport uut (
      .ClkToFPGA(clk), 
      .Reset(reset), 
      .DataValidToFPGA(dvTf), 
      .DataToFPGA(dTf), 
      .DataValidFromFPGA(dvFf),
      .DataFromFPGA(dFf)
      );

   initial
      begin
         $monitor($time, "clk = %b reset = %b dvTf = %b dTf = %b dvFf = %b dFf = %b cur_state = %h next_state = %h", 
            clk, reset, dvTf, dTf, dvFf, dFf, uut.cur_state[1:0], uut.next_state[1:0]);
      end

   initial begin
      reset = 0;
      dvTf = 0;
      clk = 0;
      dTf = 1;

// Wait 100 ns for global reset to finish
      #100 reset = 1;
      #10 reset = 0;
   end

   always begin
      #25 clk = ~clk;
   end

   always begin
      #150 dTf = 0;
      #50 dTf = 1;
      #50 dTf = 0;
      #50 dTf = 1;
      #50 dTf = 0;
      #50 dTf = 1;
      #50 dTf = 0;
   end

   initial begin
      #115 dvTf = 1;
      #370 dvTf = 0;
   end

endmodule