module transparport(ClkToFPGA, Reset, DataValidToFPGA, DataToFPGA, DataValidFromFPGA, DataFromFPGA);
   input ClkToFPGA;
   input Reset;
   input DataValidToFPGA;
   input DataToFPGA;
   output DataValidFromFPGA;
   output DataFromFPGA;

   parameter state0 = 2'b00;
   parameter state1 = 2'b01;
   parameter state2 = 2'b10;
   parameter state3 = 2'b11;
	
   wire ClkToFPGA, Reset, DataValidToFPGA;
   wire DataValidFromFPGA;
   wire DataFromFPGA;

   (* signal_encoding = "user" *)
   reg [1:0] cur_state;
   reg [1:0] next_state;
   reg [7:0] mem_ele;
   reg [2:0] bit_pos;
   wire data_out_done;
   wire inc_address;

   assign DataValidFromFPGA = (cur_state == state2 || cur_state == state3) ? 1'b1 : 1'b0;
   assign data_out_done = (bit_pos == 3'b111) ? 1'b1 : 1'b0;
   assign DataFromFPGA = mem_ele[bit_pos]; 
   assign inc_address = (cur_state == state1 || cur_state == state3) ? 1'b1 : 1'b0; 

   always @(posedge ClkToFPGA or posedge Reset)
      if (Reset == 1'b1) 
         mem_ele <= 8'b0000_0000;
      else if (DataValidToFPGA == 1'b1) 
         mem_ele[bit_pos] <= DataToFPGA;

   always @(negedge ClkToFPGA or posedge Reset)
      if (Reset == 1'b1) 
         bit_pos <= 3'b000;
      else if (inc_address == 1'b1)
         bit_pos <= bit_pos + 1;

   always @(posedge ClkToFPGA or posedge Reset) // State transition logic
      if (Reset == 1'b1) cur_state <= state0;
      else cur_state <= next_state;

   always @(cur_state or DataValidToFPGA or data_out_done) // Next state combinational logic
      begin
         case (cur_state)
            state0:
               if (DataValidToFPGA == 0)
                  next_state <= state0;
               else 
                  next_state <= state1;
            state1:
               if (DataValidToFPGA == 1)
                  next_state <= state1;
               else 
                  next_state <= state2;
            state2:
               next_state <= state3;
            state3:
               if (data_out_done == 0)
                  next_state <= state3;
               else 
                  next_state <= state0;
            default: next_state <= state0;
         endcase
      end


endmodule