This is a list of suggested topics for your semester projects. This is by no means an exhaustive list, and you are encouraged to pick a topic that you are interested in. If you're not sure whether your project is appropriate for a computer architecture class, please send me e-mail. o VHDL processor implementation. Group size of 3 or 4. Your processor must be pipelined and contain a unified cache (optionally a split instruction/data cache). In addition, it must incorpo- rate one or more of the advanced hardware pipelining techniques that we are discussing in class now and optionally one or more of the advanced cache techniques. If you chose to grab existing VHDL code for the DLX, then be prepared to modify it and conduct a thorough behavioral analysis. The alternative is to build from scratch, in which case, much less empha- sis is placed on the performance analysis, although something greater than 0 analysis is expected. The instructions (opcodes) that you are required to implement are given in a sepa- rate document on my web page. You can use any version of VHDL running on any OS as long as it is available on some machine at UMBC (since you will demonstrate your system through a simulation of a program for me near the end of the term). You can use the VHDL compiler and simulator available for the SGI machines. (See the setup instructions under VHDL under project on the 611 web page. I'll most likely do this one myself, and maybe, if enough groups participate, we'll have a contest to determine who has the highest performance design. NOTE: My VLSI students lost to me (one person vs several groups) last semester.) o Gather, analyze and compare the instruction traces of several "representative" (benchmark) programs on a CISC architecture (i.e. Pentium) and one or more RISC (i.e., Sparc, PowerPC) architectures. Are instruction set mixes different from those in the text? If so, how? NOTE: this project will involve getting tracing tools to work on a computer; you may not use down- loaded traces except to compare your traces against. o What is the maximum parallelism that a program can achieve in a perfect world? How big an instruction buffer (with out-of-order execution) is necessary to realize this parallelism, and how much parallelism can more realistic instruction buffers allow? Various options (specula- tive execution, etc.) can be added to increase potential parallelism and make the study more interesting. o Create a benchmark suite to measure some aspect of a system's performance. Why is your suite better than those that are already available? Does it give different results than existing suites? o Analyze and compare the architectures, instruction types and performance advantages of two or more graphic accelerators. What are the architectural tradeoffs among the implementations studied ? o Given a VLIW architecture and an assembly program(s), how much performance improve- ment is possible on such an architecture over existing superscaler architectures. This requires mapping the assembly program onto the VLIW architecture accounting for data, control and structural hazards as discussed in class. o Analyze cache performance in terms of miss rate under different parameters (i.e. set associa- tivity, block size), using victim caches, hardware prefetching of instructions/data and various compiler optimizations. Or methods that involve reducing cache miss penalties (see text). o Analyze the impact of virtual memory on system performance, in terms of its parameters, i.e. block size, etc, or system I/O to file systems or across networks. o Validate some analysis presented in the book or done previously in some recent research papers. I would prefer that no more than 1 (maybe 2) groups work on each project topic. There are plenty of topics here, and I expect that students will come up with many more interesting topics.