-
Improvements in CPU performance a result of:
-
Technology enhancements (already discussed).
-
Improvements in computer architecture: Innovations
-
Improvements in accompanying compilers.
-
Focus of this course is on how the second two have contributed to recent performance improvements.
-
Determine the important attributes of a new machine.
-
Maximize performance while staying within cost constraints.
-
-
Non-trivial.
-
-
Task aspects:
-
Instruction set architecture (used to be the only focus).
-
Functional organization:
-
High level aspects of computer design, i.e. memory system, bus architecture and internal CPU design.
-
Logic design (hardware)
-
Implementation (hardware)
-
Functional requirements
, cost and performance goals.
-
Former goal is difficult to determine.
-
Requires determination of application software to be used (what programs will be run ?), which may influence instruction set design.
-
Design complexity:
-
Complex designs take longer to complete (increases time-to-market).
-
Complex designs must provide higher performance to be competitive.
-
Technology trends:
-
Not only what's available today, but also what will be available when the system is ready to ship. (more on this later)
-
The amount of memory used by programs increases by a factor of
1.5
to
2
per year (1/2 to 1 address bits consumed/year) !
-
Underestimating this is often the major reason an instruction set architecture must be abandoned.
-
An increase in compiler dependency:
-
Compilers have become the primary interface between the user and machine (migration from assembly to high level languages).
-
Compilers are relied upon to transform code to improve pipeline behavior and memory system behavior.
-
How does compiler usage influence your design ?
-
Implementation technology:
-
IC Technology:
-
Feature size reduced by 30% every 3 years, doubling density every 3 years (33% more transistors/unit area/year w.r.t 1st year).
-
Die size increases necessary to achieve 59% more transistors/chip/year, in accordance with
Moore's law:
-
Number of functions doubled every 1.5-2 years.
-
Challenge: Cost/function reduction of 25-30%/year.
-
DRAM (memory):
-
Cycle time improvements are
slow
, decreasing by ~1/3 in 10 years.
-
Remember, bandwidth is proportional to cycle time and the width of the data path.
-
Implementation technology:
-
Disk technology:
-
Density improves by 25%/yr (~2x in 3 years).
-
Bandwidth increases by 25%/yr, which is proportional to the square root of density (and to rotation speed, which increases very slowly).
-
Access (seek) time increases
slowly
, 1/3 in 10 years.
-
Conclusion:
-
The designer must take these improvements into account and design for a future technology.
-
By the time the system ships, the future will be the present and the design MUST be optimal for this technology in order to be competitive.
-
Cost trends:
-
Understanding trends in component costs (how they will change over time) is an important issue for designers.
-
Remember, you design for tomorrow and what's NOT affordable today may be affordable tomorrow.
-
Observation 1:
-
Component prices drop over time without major improvements in manufacturing technology.
-
Why ?
-
The
learning curve
.
-
Consider yield (the number of good devices/total number of devices).
-
In general, a chip, board or system with
twice
the yield will have
half
the cost.
-
Problem: The learning curve is different for different components. This complicates new system design decisions.
-
Observation 2
:
-
Volume.
-
Larger volume increases rate of the learning curve. (Products get cheaper to manufacture more quickly).
-
Volume decreases cost due to increases in manufacturing efficiency.
-
Development cost amortization allows cost to get closer to selling price.
-
Therefore, The more you make, the less it costs !
-
The bigger the die, the higher its cost since "Dies/wafer" gets smaller.
-
What about yield (the number of good dies/wafer) ? A simple model:
-
"Wafer yield" accounts for wafers that are completely bad.
-
This model assumes defects are randomly distributed. In 1995, it was between 0.6 to 1.2 per cm
2
.
-
(Learning curve allows us to reduce this value over time).
-
`alpha' corresponds to the number of masking levels (complexity). It is approximately 3.0 today.
-
What is the yield assuming 100% wafer yield, 0.8/cm
2
defect density and a die size of 1.5 cm ?
-
Bottom line:
-
The number of good dies/wafer = dies/wafer * die yield.
-
The larger and/or more complex the chip, the more costly - its NOT a
linear
relationship.
-
The designer controls only the die size:
-
Decides which features/functions are included and which are excluded.
-
A decision not to be taken lightly because:
-
A strong incentive to reduce feature size, instead of increasing die size.
-
Direct
cost:
-
Costs incurred to make a single item. Adds 20% to 40% to component cost.
-
Gross margin (
Indirect
cost):
-
Overhead not associated with a single item, i.e. R&D, marketing, manufacturing equipment, taxes, etc.
-
Average Selling Price
(ASP):
-
Component cost + direct cost + indirect cost.
-
List price
:
-
Not ASP. Stores add to the ASP to get their cut. Want 50% to 75% of list price.
-
Cost goes through a number of changes before it becomes price.
-
This gives you insight on how a design decision will affect selling price,
-
i.e. changing cost by $1,000 increases selling price by $3,000 to $4,000.
-
Also, consider volume and price relationship:
-
In general, the fewer computers that are sold, the higher the price.
-
Also, a decrease in volume causes cost to increase, further increasing price.
-
-
Therefore, small changes in cost can have an
unexpected
large increase in price.
