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Understanding compiler technology is critical to designing an effective instruction set.
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Assembly language programming has been largely replaced by compilers which work together with the hardware to optimize performance.
-
Therefore,
design architectures to be compiler targets
.
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What features of an architecture lead to high quality code ?
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What "makes it easy" to write efficient compilers for an architecture ?
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Structure of recent optimizing compilers:
-
Instruction set properties that help the compiler writer:
-
Regularity
:
-
The 3 primary components of an instruction set;
operations
,
data types
and
addressing modes
should be
orthogonal
(independent).
-
Consider operations and addressing modes:
-
They are orthogonal if any address mode can be used for any operation.
-
No dependencies, i.e. MOV instruction applicable only to register mode or even worse, to only a subset of the registers.
-
Provide primitives, not solutions
:
-
Providing special features that "match" language constructs is NOT a good idea.
-
These features may be good only for a certain language.
-
And, worse, they may match but do more or less than what's required.
-
Instruction set properties that help the compiler writer:
-
Simplify trade-offs among alternatives
:
-
If there are 20 ways to implement an instruction sequence, it makes it difficult for the compiler writer to choose which is the most efficient.
-
Particularly, if each varies in cost.
-
Cache and pipelining further complicate choosing among the alternatives.
-
Allow constants to be constants
:
-
The compiler should be able to specify a constant at compile time.
-
The CPU should NOT have to
dynamically interpret
a value that was known when the program was compiled.
-
Instructions should be provided that bind the quantities known at compile time and not force run time bindings.
-
Summary:
KEEP IT SIMPLE
. Less is more in the design of an instruction set.
-
Read the section on the DLX.
-
-
Some of the DLX ISA characteristics:
-
Simple Load/Store architecture.
-
Fixed instruction encoding.
-
Minimal instruction set with 32 GPRs, R0 is always 0.
-
2 addressing modes:
-
Displacement and immediate, with 16-bit fields
-
Register deferred addressing possible using a displacement of 0.
-
Absolute addressing possible using R0 as the base.
-
Do not design an instruction set oriented towards a specific HLL.
-
Attempts to reduce the semantic gap may result in the semantic clash !
-
Instruction mismatch is likely, in which
special
instructions do more work than is required for the
frequent
case.
-
There is no such thing as a typical program.
-
Programs can vary significantly in how they use an instruction set.
-
Many times it is meaningless to average frequency criteria over several programs.
-
i.e. the mix of data transfer sizes.
-
Figure 2.31 shows a large variation among the SPEC92 benchmarks.
-
An architecture can have flaws and still be successful.
-
i.e.
80x86
: The architecture is pretty ugly !
-
Used segmentation, everyone else used paging.
-
Used extended accumulators, others used GPRs.
-
Used stack for floating point, everyone else abandoned execution stacks.
-
You can NOT design a flawless architecture !
-
Every ISA involves trade-offs.
-
You can no more make an architecture flawless than make a program perfect.
-
If it does one thing well, it may have to do something else more poorly.
-
Also, it's difficult to predict technology trends ten or more years out.
-
Consider the future expectation of memory requirements in 1980.
-
Almost all architectures succumb to lack of sufficient address space.
