Multi-Cycle Pipeline Operations

Multi-Cycle Pipeline Operations

It is not practical to require FP operations to finish in one cycle.
Or even two.

Doing so would require:

Slow clock or
Enormous amounts of logic.

Instead, we allow a longer latency for FP operations.

It is common to have several floating point units, i.e., FP Adder, FP divider.

Each of these may take multiple clocks per operation.
If they are not pipelined, structural hazards can occur.

One possible way to implement an FP pipeline is to allow the EX stage to repeat as many times as necessary.

Multi-Cycle Pipeline Operations

Consider the following (non-pipelined EX) modification to the DLX:

If an instruction cannot issue because of a structural hazard, the entire pipeline stalls.

Multi-Cycle Pipeline Operations

Let's add pipelining to some of these FP functional units.

First we need to define the latency and the initiation interval for these FP units.

Latency is the number of cycles beyond the first that is required.

The reason for this latency definition is that the integer ALU has its result ready at the end of the cycle in which it started.

In other words, it required 0 additional EX stages.

The initiation interval is the number of cycles that must elapse between instruction issue to the same unit.

For pipelined units, this interval is 1.

Therefore, FP pipelined units may have multiple outstanding operations, which are initiated every cycle.

Multi-Cycle Pipeline Operations

Assume the following latencies and initiation intervals:

Functional Unit	Latency	Initiation Interval	# of pipe stages
Integer ALU	0	1	1
Data memory (int and FP loads)	1	1	1
FP Add	3	1	4
FP and integer multiply	6	1	7
FP and integer divide	24	25	1

Integer ALU

0 cycle latency, pipelined: Result can be used on next clock cycle.

Data memory

1 cycle latency, pipelined: Result can be used after one intervening cycle.

FP add: 3 cycle latency, pipelined
FP/integer multiplier: 6 cycle latency, pipelined
FP/integer divide and FP square root: 24 cycle latency, non-pipelined

Multi-Cycle Pipeline Operations

Pipeline that supports multiple outstanding FP operations:

Note that the forth instruction after the add can use the result of an FP Add.

Multi-Cycle Pipeline Operations

Pipeline characteristics:
Structural hazards can occur for the divide unit.

The number of register writes that occur in one cycle can be greater than 1 .

Several instructions can reach WB in a single cycle because of variable length instructions.
This could cause a structural hazard if the CPU can only write one register per cycle.

Instructions no longer necessarily complete in the order in which they were issued ( Out-of-order completion .)

WAW hazards are now possible and must be detected.
This also causes problems with exceptions .

Our exception handling mechanism relied on the fact that instructions completed in the order in which they were issued.

Since instructions have longer latencies, stalls for RAW operations will be more frequent.

Multi-Cycle Pipeline Operations

RAW hazards:

MULTD stalls due to load latency.

ADDD stalls until multiply produces F0 value, which is forwarded.

SD stalls in MEM waiting on result from ADDD

Multi-Cycle Pipeline Operations

Assume FP register file has one write port.

The single write port represents a structural hazard.

This can be solved by:
Increasing the number of write ports. Not worth it since steady state usage is close to 1.
Serialize the writes.

Multi-Cycle Pipeline Operations

Solving the write port structural hazard through serialization can be done in two ways ( Implementing the interlock ):

Stall the instruction when it tries to enter the MEM or WB stage.

Advantage: It's easy to detect the conflict at this point (unlike second solution.)
Disadv: It complicates pipeline control since stalls can now occur in two places.

Keep track of when each instruction will use the WB stage and stall instructions in ID if their "slot" is already in use.

This can be done using a shift register, that tracks when already-issued instructions will use the register file.

Advantage: Instructions are stalled only in ID.
Disadv: Requires additional hardware (shift register and write conflict logic).

Multi-Cycle Pipeline Operations

Consider situation if LD issued one clock earlier (see slide 8).

We end up with a WAW hazard since LD writes F2 one cycle earlier then ADDD.

Note that this is ONLY a hazard when ADDD is overwritten without any instruction ever using it -- it appears to be a useless instruction.

If there was a use between ADDD and LD, then a RAW hazard would stall the pipeline and the WAW would not occur.

However, we must still detect them since they do occur in reasonable code (as we will see).

Multi-Cycle Pipeline Operations

Solving the WAW hazard can be accomplished in two ways:

Stall an instruction that would "pass" another until after the earlier instruction reaches the MEM phase.
Cancel the WB phase of the earlier instruction.

Both of these can be done in ID, i.e. when LD is about to issue.

Since pure WAW hazards are not common, either method works.
Pick the one that simplest to implement.

The simplest solution for the DLX pipeline is to hold the instruction in ID if it writes the same register as an instruction already issued.

Multi-Cycle Pipeline Operations

What other hazards are possible ?

Hazards among FP instructions.

Hazards between an FP instruction and an integer instruction.

Since two register files exist, only FP loads and stores and FP register moves to integer registers involve hazards.

Let's assume all hazards are detected during ID.

Three checks are required in ID (before instruction issue):

Check for structural hazards .

The divide unit.
Register write port.

Multi-Cycle Pipeline Operations

Instruction issue checks:

Check for RAW hazards

The CPU simply stalls the instruction at ID stage until:

Its source registers are no longer listed as destinations in any of the execution pipeline registers (registers between stages of M and A) OR
Its source registers are no longer listed as the destination of a load in the EX/MEM register.

Check for WAW hazards

Check instructions in A1, ..., A4, Divide, or M1, ...,M7 for the same destination register (check pipeline registers.)
Stall instruction in ID if necessary.

Note that instructions after the current one might have been able to execute, but they'll all have to wait (at least until the next chapter...).