Instructor:
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Professor Jim Plusquellic
Text:
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Computer Architecture: A Quantitative Approach,
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by John L. Hennessy and David A. Patterson.
Supplementary texts:
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Logic and Computer Design Fundamentals
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by M. Morris Mano and Charles R. Kime.
Further Info:
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http://www.cs.umbc.edu/~plusquel/611/index.html
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To introduce many of the methods used by designers to implement general purpose processors and computer systems in general (CPU, I/O, memory and networks).
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To introduce methods of analyzing CPU performance, in order to identify bottlenecks.
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To expose you to various characteristics of today's architectures, i.e. Pentium/Merced, PowerPC, DEC Alpha, Sun SPARC, HP PA-RISC, MIPS, ...
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Predominant technology: CMOS (Complimentary Metal Oxide Silicon)
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Technology generation defined by:
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Feature size: Size of the smallest features on an IC, usually the length of the transistor channel.
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Current feature size: 250 nm.
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What are the leading obstacles in reducing feature size ?
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Photolithographic tools:
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Current optical techniques: 248 nm wavelength can reduce feature size to 180 nm.
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Next (and probably last) generation of optical lithography: 193 nm wavelength can reduce feature size to 130 nm, possibly down to 100 nm.
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Contending solutions for 100 nm and below - see
Spectrum
, "Solid state", Jan. 1998).
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Wires or interconnect: Currently aluminum
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Problems:
-
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Recently, IBM Corp. and Motorola Inc., Schaumburg, Ill. independently discovered way of replacing aluminum with copper.
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Advantages:
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Resistivity is 40 - 45% lower.
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Reduced capacitance since smaller wires are possible, reduce cross-talk.
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Reliability improved because of higher tolerance to electromigration.
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No stress migration occurs.
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Intel Chairman, 1965, Gordon Moore
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Moore's Law:
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# of transistors in IC will double every 18 months.
Offical Semiconductor Industry Association (SIA) Roadmap
|
|
1995
(350 nm)
|
1998
(250 nm)
|
2001
(180 nm)
|
2004
(130 nm)
|
2007
(100 nm)
|
2010
(80 nm)
|
|
DRAM (bits)
|
64M
|
256M
|
1G
|
4G
|
16G
|
64G
|
|
MPU transistors/cm
2
|
4M
|
7M
|
13M
|
25M
|
50M
|
90M
|
|
DRAM chip size (mm
2
)
|
190
|
280
|
420
|
640
|
960
|
1400
|
|
MPU chip size (mm
2
)
|
250
|
300
|
360
|
430
|
520
|
620
|
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Accurate for last 20 years.
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Will it hold for the next 15 years ? Will it fail due to physics or economics ?
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Lithographic limits, design and test complexity and/or fabrication costs.
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Moore's Law:
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Minimum transistor feature size must decrease by a factor of 0.7 every three years:
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Moore's Second Law:
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The cost of building a semiconductor fab is doubling every three to four years.
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In 1995, approximately 50 fabs in operation all over the world. Another 50 in some state of completion.
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Current cost > $1 billion
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Toshiba predicts cost of building mega-fabs may slowdown Moore's first law.
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Companies joining forces: e.g. IBM/Siemens(64Mbit technology) and IBM/Siemens/Toshiba(256Mbit) joint developments.
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Physical Limits:
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Joel Birnbaum, HP senior president of R&D, EE times quote:
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"In 2010, we will run into the physical limitation of having a fraction of an electron show up at a gate to switch the state of the transistor"
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Pentium Pro:
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Speed: 333 MHz
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Number of transistors: 7.5 million
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Supply voltage: 3.3 system, 2.8 processor
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Technology: 250 nm
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Speed: 300 MHz
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Maximum current: 14.2 Amps
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Power: 43 Watts
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System bus speed: 66 MHz
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Level 1 cache speed: 300 MHz
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Level 2 cache speed: 150 MHz
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Die size: 560 mils/side
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PowerPC (604e):
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Speed: 250 MHz
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Number of transistors: 5.1 million
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Supply voltage: 3.3 system, 1.9 processor
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Technology: 250 nm
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Power: 6 Watts
