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-- Company: 
-- Engineer: 
-- 
-- Create Date: 08/26/2015 04:11:09 PM
-- Design Name: 
-- Module Name: full_adder - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity full_adder is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           Cin : in STD_LOGIC;
           Cout : out STD_LOGIC;
           sum : out STD_LOGIC);
end full_adder;

architecture Behavioral of full_adder is

   signal n_c: std_logic;
    signal n_d: std_logic;
    signal n_e: std_logic;

   attribute keep: string;
   attribute keep of n_c: signal is "true";
   attribute keep of n_d: signal is "true";
   attribute keep of n_e: signal is "true";

   attribute S: string;
   attribute S of n_c: signal is "true";
   attribute S of n_d: signal is "true";
   attribute S of n_e: signal is "true";
begin

   n_c <= a xor b;
   n_d <= Cin and n_c;
   n_e <= b and a;
   sum <= Cin xor n_c;
   Cout <= n_d or n_e;


end Behavioral;