SET_FLAG DEBUG FALSE SET_FLAG MODE INTERACTIVE SET_FLAG STANDALONE_MODE FALSE SET_PREFERENCE devicefamily zynq SET_PREFERENCE device xc7z020 SET_PREFERENCE speedgrade -1 SET_PREFERENCE package clg484 SET_PREFERENCE verilogsim false SET_PREFERENCE vhdlsim true SET_PREFERENCE simulationfiles Behavioral SET_PREFERENCE busformat BusFormatAngleBracketNotRipped SET_PREFERENCE outputdirectory /home/research/research/FPGAs/ZED/HELP/VHDL/ClkCoreGen/ SET_PREFERENCE workingdirectory /home/research/research/FPGAs/ZED/HELP/VHDL/ClkCoreGen/tmp/ SET_PREFERENCE subworkingdirectory /home/research/research/FPGAs/ZED/HELP/VHDL/ClkCoreGen/tmp/_cg/ SET_PREFERENCE transientdirectory /home/research/research/FPGAs/ZED/HELP/VHDL/ClkCoreGen/tmp/_cg/_dbg/ SET_PREFERENCE designentry VHDL SET_PREFERENCE flowvendor Other SET_PREFERENCE addpads false SET_PREFERENCE projectname coregen SET_PREFERENCE formalverification false SET_PREFERENCE asysymbol false SET_PREFERENCE implementationfiletype Ngc SET_PREFERENCE foundationsym false SET_PREFERENCE createndf false SET_PREFERENCE removerpms false SET_PARAMETER Component_Name launch_capture_clk SET_PARAMETER Use_Freq_Synth true SET_PARAMETER Use_Phase_Alignment true SET_PARAMETER Use_Min_Power false SET_PARAMETER Use_Dyn_Phase_Shift true SET_PARAMETER Use_Dyn_Reconfig false SET_PARAMETER Jitter_Sel No_Jitter SET_PARAMETER Use_Spread_Spectrum false SET_PARAMETER Use_Spread_Spectrum_1 false SET_PARAMETER Prim_In_Freq 100.000 SET_PARAMETER In_Freq_Units Units_MHz SET_PARAMETER In_Jitter_Units Units_UI SET_PARAMETER Relative_Inclk REL_PRIMARY SET_PARAMETER Secondary_In_Freq 100.000 SET_PARAMETER Jitter_Options UI SET_PARAMETER Clkin1_UI_Jitter 0.010 SET_PARAMETER Clkin2_UI_Jitter 0.010 SET_PARAMETER Prim_In_Jitter 0.010 SET_PARAMETER Secondary_In_Jitter 0.010 SET_PARAMETER Clkin1_Jitter_Ps 100.0 SET_PARAMETER Clkin2_Jitter_Ps 100.0 SET_PARAMETER Clkout2_Used true SET_PARAMETER Clkout3_Used false SET_PARAMETER Clkout4_Used false SET_PARAMETER Clkout5_Used false SET_PARAMETER Clkout6_Used false SET_PARAMETER Clkout7_Used false SET_PARAMETER Num_Out_Clks 2 SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI true SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false SET_PARAMETER primary_port CLK_IN1 SET_PARAMETER CLK_OUT1_port CLK_OUT1 SET_PARAMETER CLK_OUT2_port CLK_OUT2 SET_PARAMETER CLK_OUT3_port CLK_OUT3 SET_PARAMETER CLK_OUT4_port CLK_OUT4 SET_PARAMETER CLK_OUT5_port CLK_OUT5 SET_PARAMETER CLK_OUT6_port CLK_OUT6 SET_PARAMETER CLK_OUT7_port CLK_OUT7 SET_PARAMETER DADDR_port DADDR SET_PARAMETER DCLK_port DCLK SET_PARAMETER DRDY_port DRDY SET_PARAMETER DWE_port DWE SET_PARAMETER DIN_port DIN SET_PARAMETER DOUT_port DOUT SET_PARAMETER DEN_port DEN SET_PARAMETER PSCLK_port PSCLK SET_PARAMETER PSEN_port PSEN SET_PARAMETER PSINCDEC_port PSINCDEC SET_PARAMETER PSDONE_port PSDONE SET_PARAMETER Clkout1_Requested_Out_Freq 75.000 SET_PARAMETER Clkout1_Requested_Phase 0.000 SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.000 SET_PARAMETER Clkout2_Requested_Out_Freq 75.000 SET_PARAMETER Clkout2_Requested_Phase 0.000 SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.000 SET_PARAMETER Clkout3_Requested_Out_Freq 100.000 SET_PARAMETER Clkout3_Requested_Phase 0.000 SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.000 SET_PARAMETER Clkout4_Requested_Out_Freq 100.000 SET_PARAMETER Clkout4_Requested_Phase 0.000 SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.000 SET_PARAMETER Clkout5_Requested_Out_Freq 100.000 SET_PARAMETER Clkout5_Requested_Phase 0.000 SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.000 SET_PARAMETER Clkout6_Requested_Out_Freq 100.000 SET_PARAMETER Clkout6_Requested_Phase 0.000 SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.000 SET_PARAMETER Clkout7_Requested_Out_Freq 100.000 SET_PARAMETER Clkout7_Requested_Phase 0.000 SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.000 SET_PARAMETER Use_Max_I_Jitter false SET_PARAMETER Use_Min_O_Jitter false SET_PARAMETER Prim_Source No_buffer SET_PARAMETER Use_Inclk_Switchover false SET_PARAMETER secondary_port CLK_IN2 SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin SET_PARAMETER Clkout1_Drives BUFG SET_PARAMETER Clkout2_Drives BUFG SET_PARAMETER Clkout3_Drives BUFG SET_PARAMETER Clkout4_Drives BUFG SET_PARAMETER Clkout5_Drives BUFG SET_PARAMETER Clkout6_Drives BUFG SET_PARAMETER Clkout7_Drives BUFG SET_PARAMETER Feedback_Source FDBK_AUTO SET_PARAMETER Clkfb_In_Signaling SINGLE SET_PARAMETER CLKFB_IN_port CLKFB_IN SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N SET_PARAMETER CLKFB_OUT_port CLKFB_OUT SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N SET_PARAMETER Platform lin64 SET_PARAMETER Summary_Strings empty SET_PARAMETER Use_Locked true SET_PARAMETER calc_done DONE SET_PARAMETER Use_Reset true SET_PARAMETER Use_Power_Down false SET_PARAMETER Use_Status false SET_PARAMETER Use_Freeze false SET_PARAMETER Use_Clk_Valid false SET_PARAMETER Use_Inclk_Stopped false SET_PARAMETER Use_Clkfb_Stopped false SET_PARAMETER RESET_port RESET SET_PARAMETER LOCKED_port LOCKED SET_PARAMETER Power_Down_port POWER_DOWN SET_PARAMETER CLK_VALID_port CLK_VALID SET_PARAMETER STATUS_port STATUS SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED SET_PARAMETER Override_Mmcm false SET_PARAMETER Mmcm_Notes None SET_PARAMETER Mmcm_Divclk_Divide 4 SET_PARAMETER Mmcm_Bandwidth OPTIMIZED SET_PARAMETER Mmcm_Clkfbout_Mult_F 39.000 SET_PARAMETER Mmcm_Clkfbout_Phase 0.000 SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false SET_PARAMETER Mmcm_Clkin1_Period 10.000 SET_PARAMETER Mmcm_Clkin2_Period 10.000 SET_PARAMETER Mmcm_Clkout4_Cascade false SET_PARAMETER Mmcm_Clock_Hold false SET_PARAMETER Mmcm_Compensation ZHOLD SET_PARAMETER Mmcm_Ref_Jitter1 0.010 SET_PARAMETER Mmcm_Ref_Jitter2 0.010 SET_PARAMETER Mmcm_Startup_Wait false SET_PARAMETER Mmcm_Clkout0_Divide_F 13.000 SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500 SET_PARAMETER Mmcm_Clkout0_Phase 0.000 SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false SET_PARAMETER Mmcm_Clkout1_Divide 13 SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500 SET_PARAMETER Mmcm_Clkout1_Phase 0.000 SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps true SET_PARAMETER Mmcm_Clkout2_Divide 1 SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500 SET_PARAMETER Mmcm_Clkout2_Phase 0.000 SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false SET_PARAMETER Mmcm_Clkout3_Divide 1 SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500 SET_PARAMETER Mmcm_Clkout3_Phase 0.000 SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false SET_PARAMETER Mmcm_Clkout4_Divide 1 SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500 SET_PARAMETER Mmcm_Clkout4_Phase 0.000 SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false SET_PARAMETER Mmcm_Clkout5_Divide 1 SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500 SET_PARAMETER Mmcm_Clkout5_Phase 0.000 SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false SET_PARAMETER Mmcm_Clkout6_Divide 1 SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500 SET_PARAMETER Mmcm_Clkout6_Phase 0.000 SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false SET_PARAMETER Override_Dcm false SET_PARAMETER Dcm_Notes None SET_PARAMETER Dcm_Clkdv_Divide 2.0 SET_PARAMETER Dcm_Clkfx_Divide 1 SET_PARAMETER Dcm_Clkfx_Multiply 4 SET_PARAMETER Dcm_Clkin_Divide_By_2 false SET_PARAMETER Dcm_Clkin_Period 10.000 SET_PARAMETER Dcm_Clkout_Phase_Shift NONE SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS SET_PARAMETER Dcm_Phase_Shift 0 SET_PARAMETER Dcm_Clk_Feedback 1X SET_PARAMETER Dcm_Startup_Wait false SET_PARAMETER Dcm_Clk_Out1_Port CLK0 SET_PARAMETER Dcm_Clk_Out2_Port CLK0 SET_PARAMETER Dcm_Clk_Out3_Port CLK0 SET_PARAMETER Dcm_Clk_Out4_Port CLK0 SET_PARAMETER Dcm_Clk_Out5_Port CLK0 SET_PARAMETER Dcm_Clk_Out6_Port CLK0 SET_PARAMETER Override_Dcm_Clkgen false SET_PARAMETER Dcm_Clkgen_Notes None SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1 SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4 SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2 SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000 SET_PARAMETER Dcm_Clkgen_Startup_Wait false SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000 SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX SET_PARAMETER Override_Pll false SET_PARAMETER Pll_Notes None SET_PARAMETER Pll_Bandwidth OPTIMIZED SET_PARAMETER Pll_Clkfbout_Mult 4 SET_PARAMETER Pll_Clkfbout_Phase 0.000 SET_PARAMETER Pll_Clk_Feedback CLKFBOUT SET_PARAMETER Pll_Divclk_Divide 1 SET_PARAMETER Pll_Clkin_Period 10.000 SET_PARAMETER Pll_Compensation SYSTEM_SYNCHRONOUS SET_PARAMETER Pll_Ref_Jitter 0.010 SET_PARAMETER Pll_Clkout0_Divide 1 SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500 SET_PARAMETER Pll_Clkout0_Phase 0.000 SET_PARAMETER Pll_Clkout1_Divide 1 SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500 SET_PARAMETER Pll_Clkout1_Phase 0.000 SET_PARAMETER Pll_Clkout2_Divide 1 SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500 SET_PARAMETER Pll_Clkout2_Phase 0.000 SET_PARAMETER Pll_Clkout3_Divide 1 SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500 SET_PARAMETER Pll_Clkout3_Phase 0.000 SET_PARAMETER Pll_Clkout4_Divide 1 SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500 SET_PARAMETER Pll_Clkout4_Phase 0.000 SET_PARAMETER Pll_Clkout5_Divide 1 SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500 SET_PARAMETER Pll_Clkout5_Phase 0.000 SET_PARAMETER dcm_pll_cascade NONE SET_PARAMETER clock_mgr_type MANUAL SET_PARAMETER primtype_sel MMCM_ADV SET_PARAMETER primitive MMCM SET_PARAMETER SS_Mode CENTER_HIGH SET_PARAMETER SS_Mod_Freq 250 SET_SIM_PARAMETER c_component_name launch_capture_clk SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)" SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase" SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" SET_CORE_NAME Clocking Wizard SET_CORE_VERSION 3.6 SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6 SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6 SET_CORE_PATH /spock/Xilinx/14.6/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6 SET_CORE_GUIPATH /spock/Xilinx/14.6/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl SET_CORE_DATASHEET /spock/Xilinx/14.6/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/doc/pg065_clk_wiz.pdf ADD_CORE_DOCUMENT ADD_CORE_DOCUMENT ADD_CORE_DOCUMENT