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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:06:55 10/21/2011 
-- Design Name: 
-- Module Name:    ClkGenCtrl - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

entity ClkGenCtrl is
   port (
      CLK_IN1: in std_logic;
      RESET_IN_DCM: in std_logic;
      psen: in  std_logic;
      psincdec: in  std_logic;
      psdone: out std_logic;
      Clk_Launch: inout std_logic;
      Clk_Capture_Select: in std_logic;
      Clk_Capture: out std_logic;
      RESET: out std_logic);
end ClkGenCtrl;

architecture beh of ClkGenCtrl is
   constant C_RST_LENGTH : natural := 24;

   component launch_capture_clk
      port
      (
      CLK_IN1           : in     std_logic;
      CLK_OUT1          : out    std_logic;
      CLK_OUT2          : out    std_logic;
      PSCLK             : in     std_logic;
      PSEN              : in     std_logic;
      PSINCDEC          : in     std_logic;
      PSDONE            : out    std_logic;
      RESET             : in     std_logic;
      LOCKED            : out    std_logic
      );
   end component;

   signal Clk_Launch_int: std_logic;
   signal Clk_Capture_int: std_logic;
   signal locked_int: std_logic;
   signal reset_int: std_logic;
   signal rst_dcm_shreg: std_logic_vector(C_RST_LENGTH-1 downto 0);

   begin

-- Instantiate the DCM. CLK_OUT1 is 100 MHz unshifted, while CLK_OUT2 is 100 MHz with fine phase shift applied
   clknetwork: launch_capture_clk
     port map(CLK_IN1=>CLK_IN1, CLK_OUT1=>Clk_Launch_int, CLK_OUT2=>Clk_Capture_int,
        PSCLK=>Clk_Launch, PSEN=>psen, PSINCDEC=>psincdec, PSDONE=>psdone, RESET=>RESET_IN_DCM, 
        LOCKED=>locked_int);

-- ***************************************************************************************************************
   BUFG_LAUNCH_MUX_INST: BUFGMUX
      port map(
         i0 => Clk_Launch_int,
         i1 => Clk_Launch_int,
         s => Clk_Capture_Select,
         o => Clk_Launch
         );
   BUFG_CAPTURE_MUX_INST: BUFGMUX
      port map(
         i0 => Clk_Launch_int,
         i1 => Clk_Capture_int,
         s => Clk_Capture_Select,
         o => Clk_Capture
         );

-- Keep reset high until DCM is locked
   reset_int <= RESET_IN_DCM or (not locked_int);

-- Keep RESET high until lock is achieved by DCM + time lag
   RST_DCM: process(reset_int, Clk_Launch)
   begin
      if (reset_int = '1') then
         rst_dcm_shreg <= (others => '1');
      elsif rising_edge(Clk_Launch) then
         rst_dcm_shreg <= rst_dcm_shreg(C_RST_LENGTH-2 downto 0) & '0';
      end if;
   end process;

-- Once 0 reaches high order bit, release reset 
   RESET <= rst_dcm_shreg(C_RST_LENGTH-1);
end beh;