--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   03/27/2014
-- Design Name:   
-- Module Name:   /home/jimp/class/HOST/project/2014/
-- Project Name:  ISE_LaunchCaptureEngine
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: LaunchCaptureEngine
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY LaunchCaptureEngine_tb IS
END LaunchCaptureEngine_tb;
 
ARCHITECTURE behavior OF LaunchCaptureEngine_tb IS 

   constant PHASE_SHIFT_LEN_NB: integer := 9;
   constant PHASE_SHIFT_RANGE: integer := 560;
   constant PHASE_SHIFT_ZEROPHASE: integer := 0;
   constant MAX_PUT_WAIT_CYCLES_LB: integer := 1;
   constant MAX_PUT_WAIT_CYCLES_NB: integer := 1;
 
--Inputs
   signal Clk_Launch : std_logic := '0';
   signal Clk_Capture : std_logic := '0';
   signal RESET : std_logic := '0';
   signal LC_start : std_logic := '0';
   signal FPA_requested_phase : std_logic_vector(8 downto 0) := (others => '0');
   signal DisableClkGating_Launch : std_logic := '0';
   signal DisableClkGating_Capture : std_logic := '0';
   signal FPA_PhaseAdjDone : std_logic := '0';
   signal REBEL_QMOutRow : std_logic := '1';
   signal TOP_cal_mode : std_logic := '0';

--Outputs
   signal Clk_Capture_Sel: std_logic;
   signal LC_ready: std_logic;
   signal REBEL_FDMode: std_logic;
   signal FPA_PhaseAdjEn: std_logic;
   signal FPA_IncDecCtrl: std_logic;
   signal ClkEn_Launch: std_logic;
   signal ClkEn_Capture: std_logic;
   signal PUT_init_val: std_logic;
   signal REBEL_launch_preset: std_logic;

   signal L_go_out: std_logic;
   signal C_go_out: std_logic;
   signal fire_clks1: std_logic;
   signal fire_clks2: std_logic;

-- Clock period definitions -- smallest Clk_LC_skew is 1.5 ns -- less than that causes the LC engine 
-- to screw up.
   constant Clk_period : time := 10 ns;
   constant Clk_LC_skew : time := 1.5 ns;

   attribute clock_signal : string;
   attribute clock_signal of Clk_Launch : signal is "yes";
   attribute clock_signal of Clk_Capture : signal is "yes";
 
BEGIN
 
-- Behavioral instantiation
--   LCEngine: entity work.LaunchCaptureEngine(beh)
--      generic map(PHASE_SHIFT_LEN_NB=>PHASE_SHIFT_LEN_NB, PHASE_SHIFT_RANGE=>PHASE_SHIFT_RANGE, PHASE_SHIFT_ZEROPHASE=>PHASE_SHIFT_ZEROPHASE, 
--         MAX_PUT_WAIT_CYCLES_LB=>MAX_PUT_WAIT_CYCLES_LB, MAX_PUT_WAIT_CYCLES_NB=>MAX_PUT_WAIT_CYCLES_NB)
--      port map (Clk_Launch=>Clk_Launch, Clk_Capture=>Clk_Capture, RESET=>RESET, LC_start=>LC_start, 
--         requested_phase=>FPA_requested_phase, DisableClkGating_Launch=>DisableClkGating_Launch, 
--         DisableClkGating_Capture=>DisableClkGating_Capture, Clk_Capture_Sel=>Clk_Capture_Sel, 
--         ready=>LC_ready, REBEL_FDMode=>REBEL_FDMode, 
--         FPA_PhaseAdjEn=>FPA_PhaseAdjEn, FPA_IncDecCtrl=>FPA_IncDecCtrl, 
--         FPA_PhaseAdjDone=>FPA_PhaseAdjDone, ClkEn_Launch=>ClkEn_Launch, ClkEn_Capture=>ClkEn_Capture,
--         REBEL_QMOutRow=>REBEL_QMOutRow, PUT_init_val=>PUT_init_val, 
--         TOP_cal_mode=>TOP_cal_mode, REBEL_launch_preset=>REBEL_launch_preset,
--         L_go_out=>L_go_out, C_go_out=>C_go_out,
--         fire_clks1=>fire_clks1, fire_clks2=>fire_clks2);

-- Post-route instantiation
   LCEngine: entity work.LaunchCaptureEngine(Structure)
      port map (Clk_Launch=>Clk_Launch, Clk_Capture=>Clk_Capture, RESET=>RESET, LC_start=>LC_start, 
         DisableClkGating_Launch=>DisableClkGating_Launch, DisableClkGating_Capture=>DisableClkGating_Capture, 
         FPA_PhaseAdjDone=>FPA_PhaseAdjDone, REBEL_QMOutRow=>REBEL_QMOutRow, TOP_cal_mode=>TOP_cal_mode, 
         Clk_Capture_Sel=>Clk_Capture_Sel, ready=>LC_ready, REBEL_FDMode=>REBEL_FDMode, 
         FPA_PhaseAdjEn=>FPA_PhaseAdjEn, FPA_IncDecCtrl=>FPA_IncDecCtrl, 
         ClkEn_Launch=>ClkEn_Launch, ClkEn_Capture=>ClkEn_Capture, PUT_init_val=>PUT_init_val, 
         REBEL_launch_preset=>REBEL_launch_preset, L_go_out=>L_go_out, C_go_out=>C_go_out,
--         fire_clks1=>fire_clks1, fire_clks2=>fire_clks2, 
         requested_phase=>FPA_requested_phase);


   Clk_Launch_process :process
      begin
         Clk_Launch <= '1';
         wait for Clk_period/2; 
         Clk_Launch <= '0';
         wait for Clk_period/2;
   end process;

-- One or the other of these:
-- 1) When Clk_LC_skew <= Clk_period/2 
   Clk_Capture_process :process
      begin
      Clk_Capture <= '0';
      wait for Clk_LC_skew;
      Clk_Capture <= '1';
      wait for Clk_period/2;
      Clk_Capture <= '0';
      wait for Clk_period/2 - Clk_LC_skew;
   end process;

-- 2) When Clk_LC_skew > Clk_period/2 
--   Clk_Capture_process :process
--      begin
--      Clk_Capture <= '1';
--      wait for Clk_LC_skew - Clk_period/2;
--      Clk_Capture <= '0';
--      wait for Clk_period/2;
--      Clk_Capture <= '1';
--      wait for Clk_period/2 - (Clk_LC_skew - Clk_period/2);
--   end process;

   stim_proc: process
      begin		
      FPA_requested_phase <= std_logic_vector(to_unsigned(1, PHASE_SHIFT_LEN_NB));

-- When '0', this allows the latch to work normally and respond to clock signals (they force the
-- assertion of the ClkEn_xxx signals).
      DisableClkGating_Launch <= '0';
      DisableClkGating_Capture <= '0';
      FPA_PhaseAdjDone <= '0';
      REBEL_QMOutRow <= '1';
      TOP_cal_mode <= '0';
      LC_start <= '0';

-- Be sure to hold reset high for a while. 
      RESET <= '1';
      wait for Clk_period*25;
      RESET <= '0';
      wait for Clk_period*5;

-- idle 
      LC_start <= '1';
      wait for Clk_period;
      LC_start <= '0';

-- adjust_phase and adjust_done1
      wait for Clk_period*2 + 1 ns;
      FPA_PhaseAdjDone <= '1';

-- adjust_done2 
      wait for Clk_period;
      FPA_PhaseAdjDone <= '0';

-- change_capture_phase
      wait for Clk_period;

-- wait_PUT_init_val
      wait for Clk_period;

-- fire_LC_clks
      wait for Clk_period;

-- L_go_hold, complete_launch, return_launch_clk, LC_complete

      wait;
   end process;
 

END;