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-- Company: 
-- Engineer: 
-- 
-- Create Date:    
-- Design Name: 
-- Module Name:    REBEL - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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-- =====================================================================================
-- =====================================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

-- Standard MUXD style scan FF. We use a primitive from Xilinx library with Clk
-- enable because of the special timing requirements we have in this project.
entity MUXD_ScanFF is
   Port ( 
      D: in std_logic;
      SI: in  std_logic;
      SE: in  std_logic;
      CLK: in std_logic;
      ClkEn: in std_logic;
      RESET: in std_logic;
      Q: out  std_logic);
end MUXD_ScanFF;

architecture beh of MUXD_ScanFF is
   signal FF_in : std_logic;
   begin

-- MUX-D style scan FF
   with SE select
      FF_in <= SI when '1',
               D when others;

   ScanEle: FDCE
      generic map (
         INIT => '0') -- Initial value of register ('0' or '1')
      port map (
         Q => Q, -- Data output
         C => CLK, -- Clock input
         CE => ClkEn, -- Clock enable input
         CLR => RESET, -- Asynchronous clear input
         D => FF_in -- Data input
      );

end beh;


-- =====================================================================================
-- =====================================================================================
-- This module creates an entire row of MUXD style scan FFs with ClkEnable to 
-- handle launch-capture strobe requirements in this project. All elements are
-- kept close in the layout using 'RLOC' 
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity MUXD_ScanFF_Row is
   generic(
      NUM_SFFs: integer:= 8); 
   Port ( 
      D: in std_logic_vector(NUM_SFFs-1 downto 0);
      SI: in  std_logic;
      SE: in  std_logic;
      CLK: in std_logic;
      ClkEn: in std_logic;
      RESET: in std_logic;
      SO: out  std_logic;
      Q: out  std_logic_vector(NUM_SFFs-1 downto 0));
end MUXD_ScanFF_Row;

architecture beh of MUXD_ScanFF_Row is
   signal QL : std_logic_vector(NUM_SFFs downto 0);

--   attribute RLOC: string;

   begin

-- Connect high order + 1 QL to SI
   QL(NUM_SFFs) <= SI;

-- Instantiate the remaining ScanFFs. Keep all elements of the row close in the layout.
   GEN_SFF: for I in NUM_SFFs-1 downto 0 generate
--      attribute RLOC of MUXDScanFFEle:label is "X0Y" & integer'image(2*I);
      begin
      MUXDScanFFEle: entity work.MUXD_ScanFF(beh)
         port map (D=>D(I), SI=>QL(I+1), SE=>SE, RESET=>RESET, CLK=>CLK, ClkEn=>ClkEn, Q=>QL(I));
   end generate GEN_SFF;

-- Connect the QL local outputs to the port.
   Q <= QL(NUM_SFFs-1 downto 0);
   SO <= QL(0);
   
end beh;