NET "TopModule/CLK_IN" TNM_NET = "CLK_IN";
TIMESPEC "TS_CLK_IN" = PERIOD "CLK_IN" 10.000 ns HIGH 50%;

#INST TopModule/AES/REBELRow TNM = LATCHES latchgroup;
#TIMESPEC TS_REBEL_OUTPUTS = FROM latchgroup TIG;

#INST "TopModule/AES/REBELRow/REBEL_ScanEle/MuxScanFF/U0" TNM = REBEL_OUTPUT1;
#TIMESPEC TS_REBEL_OUTPUT1 = FROM REBEL_OUTPUT1 TIG;

# Disable timing along delay chain
INST "TopModule/AES/REBELRow/GEN_SFF[*].REBEL_ScanEle2/MuxScanFF/U0" TNM = REBEL_QMOUTPUTS;
TIMESPEC TS_REBEL_QMOUTPUTS = FROM REBEL_QMOUTPUTS TIG;

# Disable timing along scan path -- tools thinks it is possible to enter delay chain from scan path
INST "TopModule/AES/REBELRow/GEN_SFF[*].REBEL_ScanEle2/MuxScanFF/U1" TNM = REBEL_QOUTPUTS;
TIMESPEC TS_REBEL_QOUTPUTS = FROM REBEL_QOUTPUTS TIG;