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-- Company: 
-- Engineer:
--
-- Create Date:   12:42:21 04/03/2014
-- Design Name:   
-- Module Name:   /home/research/research/FPGAs/ZED/HELP//Top_tb.vhd
-- Project Name:  ISE_TOP
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Top
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Top_tb IS
END Top_tb;
 
ARCHITECTURE behavior OF Top_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Top
    PORT(
         GCLK : IN  std_logic;
         BTNC : IN  std_logic;
         LD0 : OUT  std_logic;
         LD1 : OUT  std_logic;
         LD2 : OUT  std_logic;
         LD3 : OUT  std_logic;
         LD4 : OUT  std_logic;
         LD5 : OUT  std_logic;
         LD6 : OUT  std_logic;
         LD7 : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal GCLK : std_logic := '0';
   signal BTNC : std_logic := '0';

 	--Outputs
   signal LD0 : std_logic;
   signal LD1 : std_logic;
   signal LD2 : std_logic;
   signal LD3 : std_logic;
   signal LD4 : std_logic;
   signal LD5 : std_logic;
   signal LD6 : std_logic;
   signal LD7 : std_logic;

   -- Clock period definitions
   constant GCLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Top PORT MAP (
          GCLK => GCLK,
          BTNC => BTNC,
          LD0 => LD0,
          LD1 => LD1,
          LD2 => LD2,
          LD3 => LD3,
          LD4 => LD4,
          LD5 => LD5,
          LD6 => LD6,
          LD7 => LD7
        );

   -- Clock process definitions
   GCLK_process :process
   begin
		GCLK <= '0';
		wait for GCLK_period/2;
		GCLK <= '1';
		wait for GCLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		

      BTNC <= '1';
      wait for 100 ns;	
      BTNC <= '0';

      wait for GCLK_period*10;



      wait;
   end process;

END;