This file describes the new features in the Xilinx® ISE Design Suite 10.1 software release. It contains the following sections:
Note: To dismiss this page uncheck Open What's New document at the startup under the ISE Edit > Preferences dialog box.
New for 10.1, streaming videos are available to assist in getting the most out of the ISE Design Suite, including the following topics. The streaming videos can be viewed at http://www.xilinx.com/design.
Introduction to PinAhead
Introduction to ExploreAhead
Introduction to Partial Reconfiguration
Get the Most Out of Your Design Using XST Synthesis Strategies
Reduce FPGA Verification Time Using New Simulation Features
Improve Productivity Using Multiple Constraint Files
Simplify Entry and Analysis of I/O Timing Constraints
Improve Time-to-Market Using Partitions and SmartGuide
Improve DSP and Embedded Design Productivity
Optimize FPGA Performance Using Goals, Strategies, and SmartXplorer
Improve Productivity Using the EDA Standard Tool Command
Language (Tcl)
Fine-Tune FPGA Power Budgets Using New Power Analysis and Optimization
Improve Configuration Ease of Use with Project Navigator and iMPACT
Xilinx has made a subset of the powerful PlanAhead
capabilities available to all ISE users by introducing PlanAhead Lite
as a part
of the standard 10.1 ISE release. This environment is installed
automatically
with ISE. It provides the I/O pin planning capabilities included in the
new
PinAhead environment. It also includes some design analysis and
floorplanning capabilities
as well as implementation control with the ExploreAhead environment.
For more
details, see the PlanAhead section.
Note: Not all of the
following devices are included in ISE WebPACK
CPLD Families: Coolrunner™-II, Coolrunner™ XPLA3, XC9500, XC9500XL, XA9500XL, XC9500XV, ACR2
Virtex Families: Virtex™-5, Virtex™-4, Virtex™-II Pro,
Virtex™-II,
Virtex™, Virtex™-E, Virtex™-EM, Q-Pro Virtex™-II, Q-Pro Virtex™-2.5V
Spartan Families: Spartan™-3, Spartan™-3E, Spartan™-3A, Spartan™-3AN, Spartan™-3A DSP
Microsoft Windows® XP Professional (32-bit and 64-bit)
Microsoft Windows® Vista Business (32-bit and 64-bit)
Red Hat Enterprise Linux 4 WS (32-bit and 64-bit)
Red Hat Enterprise Linux 5 Desktop (32-bit and 64-bit)
SUSE Linux Enterprise 10 (32-bit and 64-bit) Note: SUSE Linux Enterprise 10 Desktop Server products are binary compatible.
This section describes the new features in the Xilinx® Integrated Software Environment (ISE) 10.1 software release.
Design Goals and Strategies – Goal-based Implementation: Design Goals and Strategies can be used to achieve your particular design goals by easily controlling implementation options based on desired goals such as Power Reduction, Area Optimization, and Runtime Reduction or Timing Performance. In addition to using Goals and Strategies delivered with the ISE software, you may also create your own using the Design Strategy Editor. To access Design Goals and Strategies, select Project > Design Goals & Strategies.
Tcl Script Generation: Project Navigator can generate a Tcl script that contains all the necessary Tcl commands to create, modify, and implement your project from a Tcl command prompt. To generate this script, select Project > Generate Tcl Script…
Multi-file select: Multiple source files may be selected in the Sources View using standard Shift-Click functionality.
Multiple UCF: Supports multiple constraint files (UCF) in a single project.
Simply add each UCF file as additional source files to the ISE project.
There are no restrictions on what you can put in each file, but you could choose to organize them by type. For example, timing constraints, I/O constraints, and floorplanning constraints.
Files Tab: The Files tab in the Sources View contains a list of all source files in the project, listed in alphabetical order.
Project Navigator and System Generator integration: System Generator modules are now supported as source-types in Project Navigator.
A new file type, .sgp is now generated by System Generator and
that file can be added to Project Navigator using the Project > Add
Source command.
A single module, represented by a System Generator
icon will
then be added into your Project Navigator project.
SmartGuide – user may select desired NCD to use as
guide file: SmartGuide may
be enabled by right-clicking on the top-level source file in the
Sources View, and selecting SmartGuide > Use SmartGuide. Now
you may optionally specify any previously implemented NCD file as the
guide file. By default, the most recently implemented NCD file
will be used as the guide file.
SmartXplorer integrated in Project Navigator (Linux
only): SmartXplorer allows you to run multiple implementation runs
in parallel on multiple machines, using varying pre-defined sets of
implementation options to attempt to achieve timing on your
design. SmartXplorer can be invoked through Project Navigator by
selecting Project > SmartXplorer > Launch SmartXplorer.
Automatic brace matching and bookend feature.
New Reports:
New Module-based Resource Utilization Report: available in
easy-to-view table format from Design Summary.
New Physical Synthesis Report available.
Partition Report improvements: new fields reflect new
information provided by MAP and Pack.
Design Summary Improvements:
Collapsible tables within Summary: expand and compress
individual
tables to view chosen sections of the report.
More apparent indication of errors: failing constraints,
unroutes, non zero timing score are now flagged to be noticed
immediately.
Improved layout: most important information now positioned at
top of page.
Show and Hide selection: easily customize reports list for
which
reports you wish to view.
Print preview now available for text reports.
View Report as HTML: new right-click command for text-based
message and report views.
Messages:
Message filtering dialog has larger fields for easier editing.
Message selection for filtering: you can select multiple
messages and quickly create multiple filters. Useful also for multiple
tagging and highlighting selections.
Error message text improvement: hard-to-understand messages
have been rewritten with better explanation of problem and solution.
Cross probing from messages to HDL Editor.
Message filtering support for Generate Power Data
process.
New Macro inference capabilities:
SRL inference for shift register with single set or reset signal.
Simple dual-port distributed RAM inference.
Virtex™-5 Area reduction switches:
LUT Combining (-lc) combines two LUTs into one dual-output LUT6 site.
Reduce Control Sets (-reduce_control_sets) remaps control signals (clock enable, synchronous set/reset) to the data input of a register to alleviate packing congestion.
The Netlist Hierarchy feature allows users to rebuild the design hierarchy even after the design has been flattened during synthesis.
New LUT Combining switch (-lc) improves area utilization for Virtex™-5 designs.
Performance and runtime improvement for Virtex™-5 architectures.
Both MAP and PAR now support two timing modes:
Performance Evaluation Mode sets up automatic timing constraints to evaluate the peak performance for a design.
Non Timing Driven Mode ignores all timing constraints to process the design as quickly as possible.
A new value for the IOB constraint has been introduced: FORCE
The environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING has been replaced by the local constraint CLOCK_DEDICATED_ROUTE.
Report Improvements:
New Physical Synthesis Report details register optimizations during Global Optimization and Timing-Driven Packing and Placement phases.
MAP Report shows device utilization by hierarchy.
DCM and PLL reporting has been enhanced.
SmartXplorer allows you to run multiple implementation runs in parallel on multiple machines, using varying pre-defined sets of implementation options to attempt to achieve timing on your design.
SmartXplorer can be invoked through Project Navigator by
selecting Project > SmartXplorer > Launch SmartXplorer or at the
command prompt by invoking smartxplorer.
Partition preservation has been
enhanced so that modifications to timing constraints will cause only
the affected Partitions to be re-implemented.
Ability to set a Partition on a CORE Generator™ (.xco) module.
Ability to set a Partition on a Xilinx Platform Studio (.xmp)
module.
Supports multiple constraint files
(UCF).
Can now be launched in standalone mode for all device families including Virtex™-5, a pre-existing ISE project is not required to use Floorplan Editor. Simply use the pace command from the command prompt or launch it from the Xilinx program group (Accessories menu).
Supports multiple constraint files (UCF) enabling arbitrary categorization of constraints including separation of physical and timing constraints.
Added the Input Timing Wizard for the easy creation and modification of input interface timing constraints.
Supports use of the new RISING and FALLING keywords for the OFFSET IN and OFFSET OUT constraints simplifying dual data rate (DDR) interface constraints.
Supports use of the new REFERENCE_PIN keyword for the OFFSET OUT constraint enabling improved bus-based output skew reporting for source synchronous interfaces.
Added endpoint analysis to group path reporting by destination synchronous element to increase timing closure capabilities.
Provides enhanced bus-based skew reporting for source synchronous output interfaces.
Added timing constraint interaction report enabling improved constraint analysis capabilities.
Command Coverage:
Tcl support included for all ISE process properties.
New property support includes those used by the processes: Generate
Programming File and Generate Post-Place & Route Static Timing.
xfile remove command works with [search * -type file] as its argument, enabling use of wildcarding of files within your project.
New -view option to xfile add command, allowing you to specify any non-default view location when adding new files to your project.
Tcl support added for SmartGuide NCD guidefile name specification.
Automatic Script Creation:
Project Generate Tcl Script... function from
Project Navigator creates a Tcl script you can use to recreate your ISE
project, all properties, or changed properties.
Timing Analysis Commands Enhancements:
New timing_analysis properties subcommand displays a
list of supported properties.
New -descriptors option returns a collection of
properties. You can use this collection to programmatically iterate and
get property values.
Search Command Enhancements:
Expressions now supported as search criteria.
Search types expanded to include device types: belsite,
io_standard, site, and tile.
Search capabilities expanded to search within a specified collection.
Command Names Specification:
Underscores as well as spaces accepted for subcommand and property names.
Command-Line Help:
The help project property
[property name] shows detailed Help for each property. This Help
information is generated dynamically from reference documentation.
Both new IP cores as well as updated IP core versions are included
in the 10.1 release.
New IP Cores:
Debug and Verification - ChipScope Pro™
All ChipScope Pro (ATC2, ICON, ILA and VIO) cores are
now available through CORE Generator™.
Full project support through CORE Generator.
Core Inserter also supports CORE Generator.
Digital Signal Processing
Discrete Fourier Transform v2.1
Video Image Processing
RGB to YCrCb Color-Space Converter v1.0.
YCrCb to RGB Color-Space Converter v1.0.
IP Core Updates:
A comprehensive listing of cores that have been updated in this release can be viewed at http://www.xiilinx.com/ipcenter/coregen/101_0_datasheets.htm.
For more information see http://www.xilinx.com/ipcenter/coregen/updates_101_ip0.htm.
New CORE Generator Features
Users will now get a warning from BitGen and iMPACT if their design contains evaluation cores that will cease to function after a certain period of time.
See the ISim Online Help at http://www.xilinx.com/support/sw_manuals/xilinx10 for detailed coverage of these topics.
Ability of the ISE Simulator (ISim) Engine to handle larger designs.
Compilation time and size cut down significantly.
Simulation Waveform Enhancements:
New Improved timescale
Grouping of signals
New Waveform Viewer available to load static waveform (.xwv file)
Hierarchy Viewer:
New Signals window (Objects tab) and Hierarchy Browser (Instances tab) Advanced search and filter ability
Advanced search and filter ability
Complete printing support
DO file conversion
Identify and display the current scope.
MXE is updated to ModelSim Xilinx® Edition III Version 6.3c.
See the Synthesis and Simulation Design Guide at http://www.xilinx.com/support/sw_manuals/xilinx10 for detailed coverage of these topics.
New IP Encryption Methodology to replace the existing SMARTmodel solution
Reduction of simulation runtimes
UniMacro Library to aid instantiation of complex device primitives used for synthesis and simulation
Support for Master SelectMAP Configuration Simulation Model for Spartan™-3A and Virtex™-5
Spartan™-3AN In-System Flash Simulation
ChipScope Pro™ is integrated into the new ISE Design Suite
All ChipScope Pro cores are available through the Xilinx CORE Generator tool
ICON, ILA, VIO, and ATC2 cores are supported (IBERT core uses custom design generation tool)
Full project support through CORE Generator
CORE Generator is part of ISE, making it easier to integrate
ChipScope Pro cores into ISE Projects
CORE Inserter also supports CORE Generator
Virtex™-5 FXT support for all ChipScope Pro tools and cores (including the Serial I/O Toolkit)
Enhancements to the Virtex™-5 System Monitor console make it easier to take on-chip temperature, voltage, and external sensor readings
New IBERT parameter sweep function for Virtex-5 RocketIO GTP and GTX transceivers.
Enables the user to specify TX and RX parameters to sweep through to find optimal RocketIO transceiver settings.
Provides a means to determine phase margin by automatically sweeping through all RX phase sampling points.
All parameter sweep results are saved to a file for post-processing.
Embedded Design Kit OS Support: Windows® XP Pro 32-bit English
Language Version.
Installs under the ISE Design Suite 10.1 unified installer.
Support for Virtex™-5 FXT devices with PPC440.
Enhanced integration with SystemGenerator DSP development tool: Now supports MicroBlaze™ v7 and PLBv46 for integration into SystemGenerator project.
Built-in support for generation of LynuxWorks BlueCAT Linux for MicroBlaze™.
Virtex™-5 hard IP blocks (PPC440, TEMAC, PCIe) simulation models will now use IP-Protect models. These models can be found in a new simulation library called secureip.
A mixed language simulation license is required to run simulations using the IP-Protect models.
The following enhancements are available in the new MicroBlaze™ version v7.10a: Optionally allows use of Xilinx Cache Link interface for all instruction and data memory accesses.
The following enhancements are available for new versions of
Processor IP Cores: MPMCv4.00.a
New Memory Interface Black (MIB) PIM for connection to PPC440 on V5FXT.
New Video Frame Buffer Controller (VFBC) PIM for streaming video applications.
Upgrade to MIGv2.1 physical interface for DDR and DDR2 memory.
SDRAM ECC support added.
This release of EDK included the following general enhancements:
Full PLBv46 IP support for Virtex™-II Pro family, including Base System Builder, updated debug support, and LWIP support.
Base System support for the Spartan™-3A DSP 3400 Development Board.
Support for RHEL3.0 Platform
If you are using Redhat Linux RHEL 3, then this is not a supported platform by either ISE or EDK. If you want to continue running it on this platform and getting the libstdc++.so not found error, manually add $XILINX/lib/lin to you $LD_LIBRARY_PATH environment variable.
The GUI menu support for Export to Project Navigator and Import from Project Navigator has been dropped. This flow has been deprecated since EDK 8.1. Customers should instantiate the embedded subsystem as a module in Project Navigator.
The XPS project setting to Optimize High Fanout reset nets is being dropped. It is recommended that users directly use the Map -register_duplication switch to get equivalent behavior.
BSB for ML310 supports the default bus frequently only which is 100MHz.
Windows® XP Pro 32-bit English Language Version (only).
System Generator and Project Navigator Integration:
System Generator designs can now be more easily incorporated into a larger design inside of Project Navigator by using a new source type in Project Navigator. The System Generator design can also be launched from Project Navigator.
DCM Support:
System Generator now provides the option to automatically include a DCM in the design. Although the optional DCM is abstracted away from the designer, the generated design will leverage DCMs available in the silicon.
An alternative option exposes the clock ports at the top level for manual connection to a DCM.
Dual Asynchronous-Clock Support for PLB46:
This capability gives the designer additional flexibility by allowing the DSP and embedded processing portions of a design to run at different clock rates.
Run Time Speed Improvements:
Up to two times faster first time initialization of a simulation.
Ten times faster initialization when loading the System Generator Blockset.
M-Based HW Co-Simulation:
System Generator models compiled for HW Co-Simulation can now be embedded, configured and used in a MATLAB M-code script; allowing for calls into hardware to be made from MATLAB.
New IP Models Added:
FFT 5.0 - Update to
existing block which now includes cyclic prefix insertion.
FIR Compiler 3.2 - Update
that now include support for Virtex™-II and Spartan™-3A.
Reset Generator - New block that produces synchronized downsampled reset signals, which eliminates the need to manually create these signals.
CIC 1.1 - New block now
available in System Generator.
Supported Third-Party Tools:
MATLAB 2007a and 2007b
Synplify Pro 8.9
ModelSim 6.3c
Native Complex Number Support
AccelDSP can now synthesize MATLAB written using the built-in complex number coding style. See the documentation for more details on supported functions. For example, the following code can now be synthesized into RTL:
function y =
my_design(x)
A = 3+4i;
y = (x + A) * -3i
/ 2;
More Efficient Mapping to BlockRAMs
Now two values can be read from a BlockRAM in a single cycle. This doubles the read throughput attainable from each BlockRAM.
Supported Third-Party Tools
MATLAB 2007a and 2007b
Synplify Pro 8.9
ModelSim 6.3c
Windows® XP Pro 32-bit English Language Version.
PlanAhead 10.1 now fully supports the Virtex™-5FXT FPGA devices. As
new devices are introduced, they will be made available in PlanAhead
through incremental 10.1x releases.
To be consistent with the rest of the Xilinx software tools, and to improve the overall user experience, the method by which that PlanAhead is released and licensed has changed dramatically with the 10.1 release.
Xilinx Common Installer:
PlanAhead is now included on the 10.1 software DVD and installed using the new Xilinx common installer. It is also available electronically using the Xilinx Electronic Fulfillment environment.
All ISE users will receive PlanAhead Lite installed automatically with the 10.1 ISE software. Refer to the PlanAhead Lite section for more information. The installer provides the ability to install the full version of PlanAhead independent of the other Xilinx software tools.
The previous ftp-based electronic download capability will be discontinued and replaced with the XilinxUpdate utility, as used in other Xilinx products.
Licensing:
To better align with the rest of the Xilinx software tools, the FLEXlm license manager has been removed from the PlanAhead tool. The 10.1 ISE software combined registration ID process will now be used to gain access to PlanAhead. Customers will receive registration IDs with PlanAhead included for each seat of PlanAhead owned or purchased.
The impact of removing FLEXlm includes losing the ability to use the floating license features. Users will be limited to the access available for all ISE software products under the Xilinx Software License Agreement.
Users will be able to register for free 60 day evaluation licenses using the common Xilinx installation and registration process.
Incremental Releases:
To be consistent with the other Xilinx software tools, the PlanAhead incremental release strategy has also changed significantly. Previously, a separate release kit was created for each incremental release. This involved a separate installation for each incremental release (9.2.1, 9.2.2, 9.2.3, etc.). PlanAhead now uses a overlay approach which involves installing the modified incremental release files on top of the current installation directory. The existing XilinxUpdate mechanism will be used to alert users of new PlanAhead releases and to download and install the updates.
Xilinx has made a subset of the powerful PlanAhead capabilities available to all ISE users by introducing PlanAhead Lite as a part of the standard 10.1 ISE release. This environment is installed automatically with ISE. It provides the I/O pin planning capabilities included in the new PinAhead environment. It also includes some design analysis and floorplanning capabilities as well as implementation control with the ExploreAhead environment.
After installation, Windows users can use the PlanAhead Desktop icon or Windows start menu to invoke the PlanAhead Lite. Linux users run the settings script or add the PlanAhead install bin directory to the search path. The planAhead command is used to invoke the tool.
PlanAhead and PlanAhead Lite are basically the same executable and environment. PlanAhead Lite will have some of the PlanAhead features disabled. For more information about the PlanAhead Lite or PlanAhead features, refer to the PlanAhead User Guide, PlanAhead Lite Tutorial or the PlanAhead Release Notes.
PlanAhead Lite Features Overview:
The PinAhead I/O pin planning environment.
Most PlanAhead analysis features – Schematic, Hierarchy, Netlist, Search, and Properties (No TimeAhead or Metrics).
The ExploreAhead implementation environment (No multiple processors or multiple host support. No Pblock implementation).
PlanAhead Features Overview:
HDL import with RTL elaboration, construct checking, resource estimation and schematic exploration.
TimeAhead static timing analysis.
The ExploreAhead environment with support for multiple processors, multiple hosts as well as Pblock implementation. This feature will be either introduced or improved in future incremental 10.1x PlanAhead releases.
Design Metrics display.
Export Pblock and IP capabilities.
PinAhead: PlanAhead 10.1 includes several enhancements to the PinAhead environment, as described below.
Automatic Prohibit of Noise Sensitive Pins: PinAhead will now automatically set prohibits on pins where appropriate. VREF pins will be selectively prohibited depending on the I/O standard applied to the I/O banks. Pins adjacent to the Gigabit Transceivers (GTs) are subject to signal noise issues. These pins are identified in the Xilinx GT documentation. PinAhead will now automatically prohibit ports from being placed on these pins as GTs are assigned or moved.
Automatic Placement Rules: Several new placement rules were added to the Automatic I/O Port Placement command to help ensure proper assignment.
DCI Cascading Constraints: PinAhead now properly supports DCI cascading constraints and will assign pins accordingly.
DRC: Several new I/O related DRC checks have been added to ensure legal I/O Port assignment.
Miscellaneous:
Manual I/O port placement is now possible by entering the pin location in the Port Properties - General dialog.
As I/O Ports are placed, the corresponding VCCo voltage value is now displayed in the Package Pins view. This helps when searching for compatible I/O Banks to place I/O ports.
The internal package routing displayed in the Package Pins view under the Trace column is now shown in increments of time rather than in length. This helps to calculate overall path delay.
Reporting:
The WASSO analysis report can now be exported to a text file by entering a file name and location in the Run WASSO Analysis dialog.
Resource utilization statistics for the design or individual modules can be exported to a file using the Save statistics to a file toolbar command in the Instance Properties view.
TimeAhead Improvements: The TimeAhead static timing analysis has been updated to better support Virtex™-5 and some Virtex™-4 designs. Previous TimeAhead versions had accuracy issues with certain logic constructs in those devices.
ExploreAhead Support for Remote Hosts: ExploreAhead 10.1 provides the ability to run the implementation on remote hosts. Users can define a set of remote hosts to have access. Upon launching runs, users can specify which machine to use for each ExploreAhead run. This feature is script based and uses the ssh command, therefore limiting availability to Linux users. Future 10.1.x improvements will include GUI support for all platforms including Windows.
RTL Import and Analysis: PlanAhead 10.1 has an RTL import, analysis features as well as the ability to launch synthesis using DesignAhead. This enables the ability to use RTL as the source for the project for an RTL to bitstream solution.
Importing RTL: PlanAhead projects can now be created using either Verilog, VHDL or both as the source. Users may browse to select individual source files or directories. If directories are selected, all relevant files within the directory are added to the project. PlanAhead can use either the original source files on disk or copy them to the PlanAhead project location. If archiving or moving projects, ensure to include the RTL source files in the Project.
HDL Editor: An HDL text editor is built into the environment with intuitive viewing and search capabilities included. Users can select from the available RTL templates in the ISE software tools to create RTL source.
RTL Analysis: PlanAhead 10.1 leverages the RTL parser supplied by Verific®. This widely used solution elaborates the RTL and performs basic legality checking. Once compiled, the design can be explored in the PlanAhead schematic and HDL editor. Cross probing and searching capabilities are provided to help identify problems in the RTL code. Look for schematic improvements in future 10.1.x releases.
Resource Estimation: After the RTL is elaborated, estimations of the resources required are provided to help users select a target device and to get a sense of the size of their designs. These are early estimations based on RTL only and may change after synthesis and implementation.
New, one-step device programming for Project Navigator users.
Capability to set programming and erase properties on a
per-device basis and save those settings with the iMPACT project.
Support for new XCF128 Xilinx parallel PROM device.
Any file can be added to a PROM file.
iMPACT now supports Spartan™-3E devices for the indirect SPI
Flash programming and erase flow.
The bitstream header has been changed to allow iMPACT to check
stepping level and IP core hardware-timeout license settings.
New Linux driver, based on LibUSB, is now available for download
from the Xilinx website. For details, see Answer Record #25249 at
http://www.xilinx.com/support/answers/25249.htm.
The Programming Tools are now provided as a separately installable item in the ISE Design Suite 10.1 Installer.
For Technical Support Issues, visit www.xilinx.com/support
where features such as the Answers Browser, Problem Solvers, and Users Forums may help to
resolve your issue. If your issue can not be resolved on the
support site, a WebCase can be created and a Technical
Support engineer can further assist you. What's New on www.xilinx.com.
For further release-specific information see the ISE 10.1 Release Notes and Installation Guide, available from the Software Manuals collection. The ISE 10.1 Release Notes and Installation Guide lists ISE 10.1 software contents and provides installation instructions.