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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:53:49 08/31/2009 
-- Design Name: 
-- Module Name:    simple_combo - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity simple_combo is
    Port ( 
         PB_UP_not : in  STD_LOGIC;
         PB_DOWN_not : in  STD_LOGIC;
         PB_LEFT_not : in  STD_LOGIC;
         PB_RIGHT_not : in  STD_LOGIC;
         LED1_OUT_not : out  STD_LOGIC);
end simple_combo;

architecture Behavioral of simple_combo is
   signal PB_UP: STD_LOGIC;
   signal PB_DOWN: STD_LOGIC;
   signal PB_LEFT: STD_LOGIC;
   signal PB_RIGHT: STD_LOGIC;
   signal LED1_OUT: STD_LOGIC;

begin

   PB_UP <= not PB_UP_not;
   PB_DOWN <= not PB_DOWN_not;
   PB_LEFT <= not PB_LEFT_not;
   PB_RIGHT <= not PB_RIGHT_not;

   LED1_OUT <= PB_UP or PB_DOWN or PB_LEFT or PB_RIGHT;

   LED1_OUT_not <= not LED1_OUT;

end Behavioral;