#  Nexys 2-1200 Board
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<7> LOC=J14  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<6> LOC=J15  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<5> LOC=K15  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<4> LOC=K14  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<3> LOC=E16  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<2> LOC=P16  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<1> LOC=E4  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LEDs_8Bit_GPIO_IO_O_pin<0> LOC=P4  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<11> LOC=L18  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<10> LOC=F18  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<9> LOC=D17  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<8> LOC=D16  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<7> LOC=G14  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<6> LOC=J17  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<5> LOC=H14  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<4> LOC=C17  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<3> LOC=F17  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<2> LOC=H17  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<1> LOC=C18  |  IOSTANDARD = LVCMOS33;
Net fpga_0_LED_7SEGMENT_GPIO_IO_O_pin<0> LOC=F15  |  IOSTANDARD = LVCMOS33;
#Net fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin<2> LOC=D18  |  IOSTANDARD = LVCMOS33;
#Net fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin<1> LOC=E18  |  IOSTANDARD = LVCMOS33;
#Net fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin<0> LOC=H13  |  IOSTANDARD = LVCMOS33;
#### Module switch_debouncer_0 constraints
Net switch_debouncer_0_INPUT_SWITCH_ARRAY_pin<0> LOC=H13; # BTN3
Net switch_debouncer_0_INPUT_SWITCH_ARRAY_pin<1> LOC=E18; # BTN2
Net switch_debouncer_0_INPUT_SWITCH_ARRAY_pin<2> LOC=D18; # BTN1
#Net switch_debouncer_0_INPUT_SWITCH_ARRAY_pin<3> LOC=B18; # BTN0
Net switch_debouncer_0_INPUT_SWITCH_ARRAY_pin<*> IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<7> LOC=G18  |  IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<6> LOC=H18  |  IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<5> LOC=K18  |  IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<4> LOC=K17  |  IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<3> LOC=L14  |  IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<2> LOC=L13  |  IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<1> LOC=N17  |  IOSTANDARD = LVCMOS33;
Net fpga_0_Switches_8Bit_GPIO_IO_I_pin<0> LOC=R17  |  IOSTANDARD = LVCMOS33;
Net fpga_0_RS232_PORT_RX_pin LOC=U6  |  IOSTANDARD = LVCMOS33  |  PULLUP;
Net fpga_0_RS232_PORT_TX_pin LOC=P9  |  IOSTANDARD = LVCMOS33  |  DRIVE = 2;
Net fpga_0_Micron_RAM_Mem_A_pin<31> LOC=J1  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<30> LOC=J2  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<29> LOC=H4  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<28> LOC=H1  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<27> LOC=H2  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<26> LOC=J5  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<25> LOC=H3  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<24> LOC=H6  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<23> LOC=F1  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<22> LOC=G3  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<21> LOC=G6  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<20> LOC=G5  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<19> LOC=G4  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<18> LOC=F2  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<17> LOC=E1  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<16> LOC=M5  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<15> LOC=E2  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<14> LOC=C2  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<13> LOC=C1  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<12> LOC=D2  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<11> LOC=K3  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<10> LOC=D1  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_A_pin<9> LOC=K6  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_OEN_pin LOC=T2  |  IOSTANDARD = LVCMOS33  |  DRIVE=2  |  PULLUP;
Net fpga_0_Micron_RAM_Mem_WEN_pin LOC=N7  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_BEN_pin<0> LOC=K4  |  IOSTANDARD = LVCMOS33  |  DRIVE=2  |  PULLDOWN;
Net fpga_0_Micron_RAM_Mem_BEN_pin<1> LOC=K5  |  IOSTANDARD = LVCMOS33  |  DRIVE=2  |  PULLDOWN;
Net fpga_0_Micron_RAM_Mem_DQ_pin<15> LOC=L1  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<14> LOC=L4  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<13> LOC=L6  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<12> LOC=M4  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<11> LOC=N5  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<10> LOC=P1  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<9> LOC=P2  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<8> LOC=R2  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<7> LOC=L3  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<6> LOC=L5  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<5> LOC=M3  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<4> LOC=M6  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<3> LOC=L2  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<2> LOC=N4  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<1> LOC=R3  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_Micron_RAM_Mem_DQ_pin<0> LOC=T1  |  IOSTANDARD = LVCMOS33  |  DRIVE=2;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC=B8  |  IOSTANDARD = LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC=B18  |  IOSTANDARD = LVCMOS33;