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-- Company: 
-- Engineer: Jim Plusquellic
-- 
-- Create Date:    16:04:58 09/23/2009 
-- Design Name: 
-- Module Name:    ALU
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

-- A and B are the 12-bit input operands and DEST_OUT is the 12-bit output operand.
-- skw_success is set under one of four conditions, whether a is gt/ls/eq/neq to b
-- the remaining xxx_ins parameters are instructions. Only ONE (or zero) will ever
-- be 1.
entity ALU is
   Port ( 
      A, B : in std_logic_vector(11 downto 0);
      DEST_OUT: out std_logic_vector(11 downto 0);
      skw_success: out std_logic;
      inv_ins: in std_logic;
      and_ins: in std_logic;
      or_ins: in std_logic;
      xor_ins: in std_logic;
      add_ins: in std_logic;
      sub_ins: in std_logic;
      shltf_ins: in std_logic;
      shrtf_ins: in std_logic;
      skwlf_ins: in std_logic;
      skwgf_ins: in std_logic;
      skwnf_ins: in std_logic;
      skwef_ins: in std_logic;
      movf_ins: in std_logic;
      movlw_ins: in std_logic
   );
end ALU;

architecture beh of ALU is
   signal carry_out : std_logic;
   signal skw1, skw2 : std_logic;
   begin

-- Adder
   AddComponent: entity work.AddUnit(beh)
      port map (add_ins=>add_ins, sub_ins=>sub_ins, skwlf_ins=>skwlf_ins, skwgf_ins=>skwgf_ins, 
         A=>A, B=>B, ADD_OUT=>DEST_OUT, skw_success=>skw1, carry_out=>carry_out);

-- Boolean operations
   BoolComponent: entity work.BoolUnit(beh)
      port map (and_ins=>and_ins, or_ins=>or_ins, inv_ins=>inv_ins, xor_ins=>xor_ins, 
         skwnf_ins=>skwnf_ins, skwef_ins=>skwef_ins, A=>A, B=>B, BOOL_OUT=>DEST_OUT, skw_success=>skw2);

-- Shifter and move operations
   ShiftComponent: entity work.ShiftUnit(beh)
      port map (shltf_ins=>shltf_ins, shrtf_ins=>shrtf_ins, movf_ins=>movf_ins, movlw_ins=>movlw_ins, 
         B=>B, SHIFT_OUT=>DEST_OUT);

   skw_success <= skw1 or skw2;

end beh;