----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Jim Plusquellic
-- 
-- Create Date:    16:04:58 09/23/2009 
-- Design Name: 
-- Module Name:    ShiftUnit
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

-- shltf_ins is one bit shift left, shrtf_ins is one bit shift right. 
entity ShiftUnit is
   port(
      shltf_ins, shrtf_ins, movf_ins, movlw_ins : std_logic;
      B : in std_logic_vector(11 downto 0);
      SHIFT_OUT : out std_logic_vector(11 downto 0)
   );
end entity;

architecture beh of ShiftUnit is
   signal one_hot_ins : std_logic_vector(3 downto 0);
   signal result : std_logic_vector(11 downto 0);
   begin

   one_hot_ins <= shltf_ins & shrtf_ins & movf_ins & movlw_ins;
   
-- Carry out the operation, left shift inserting a '0' on right, right shift preserving
-- the sign bit or no shift at all for the mov instructions
   with one_hot_ins select
      result <= B(10 downto 0) & '0' when "1000",
                B(11) & B(11 downto 1) when "0100",
                B when others;

-- The tri-state
   with one_hot_ins select
      SHIFT_OUT <= (others => 'Z') when "0000",
                 result when others;

end beh;