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-- Company: 
-- Engineer: Jim Plusquellic
-- 
-- Create Date:    16:04:58 09/23/2009 
-- Design Name: 
-- Module Name:    full_adder
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

-- a and b are 1-bit values to add, sum_out and carry_out are the results
entity FullAdder is
   port(
      a, b, carry_in : in std_logic; 
      sum_out, carry_out : out std_logic
   );
end entity;

architecture beh of FullAdder is
   signal tmp, carry_generate, carry_propagate : std_logic;
   begin
   
-- sum is '1' if 1 or 3 '1's occur in a, b and carry_in (2 '1's produces a '0' for sum)
   tmp <= a xor b;
   sum_out <= tmp xor carry_in;

   carry_generate <= a and b;

-- case in which a and b are different, 0 and 1 or 1 and 0 -- anding with
-- carry_in gives the two out of three needed for propagation
   carry_propagate <= tmp and carry_in;
   carry_out <= carry_generate or carry_propagate;
   
end beh;