----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:04:58 09/23/2009 
-- Design Name: 
-- Module Name:    UARTDriver - beh 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

-- clk and reset needed for UART state machine. tx_wire is output wire to UART connector. 
-- rx_wire is input wire from UART connector. 
entity UARTDriver_tb is
end entity;

architecture beh of UARTDriver_tb is
   constant T: time := 10 ns;
   signal clk, reset : std_logic;
   signal enter_pb, enter_pb_not : std_logic;
   signal empty, LED_0_not : std_logic;
   signal reset_too, LED_1_not : std_logic;
   signal button_level, LED_2_not : std_logic;
   signal tx_go, LED_3_not : std_logic;
   signal rx_wire : std_logic;
   signal tx_wire : std_logic;

   begin

   UARTDriverUnit: entity work.UARTDriver(beh)
      port map(clk=>clk, reset=>reset, enter_pb_not=>enter_pb_not, 
         LED_0_not=>LED_0_not, LED_1_not=>LED_1_not, LED_2_not=>LED_2_not, LED_3_not=>LED_3_not, 
         rx_wire=>rx_wire, tx_wire=>tx_wire);

   enter_pb_not <= not enter_pb;
   empty <= not LED_0_not;
   reset_too <= not LED_1_not;
   button_level <= not LED_2_not;
   tx_go <= not LED_3_not;

-- 10 ns clock
   process
      begin
      clk <= '0';
      wait for T/2;
      clk <= '1';
      wait for T/2;
   end process;

-- reset -- assert for T/2, and then 0 forever
   reset <= '1', '0' after T/2;

-- simulate sending a byte
   process
      begin
      enter_pb <= '0';
      rx_wire <= '1';

-- get past reset
      wait until falling_edge(clk);
      wait until falling_edge(clk);

-- Need to write a byte to the serial register. Write the start bit
-- NOTE: Modify UARTUnit.vhd generic 'BAUDGEN_CLOCK_TO_BAUD_MOD: integer := 651;' -- set to 2
-- instead for simulations. ALSO: in DEBOUNCE.vhd, modify 'constant N: integer:= 22;' to 2 
-- so button press -- doesn't take forever
      rx_wire <= '0';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;

-- 8 data bits -- write '00110100'
      rx_wire <= '0';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;
      rx_wire <= '0';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;
      rx_wire <= '1';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;
      rx_wire <= '1';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;
      rx_wire <= '0';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;
      rx_wire <= '1';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;
      rx_wire <= '0';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;
      rx_wire <= '0';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;

-- Stop bit
      rx_wire <= '1';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;

-- push the button and watch the tx wire
      enter_pb <= '1';
      for i in 1 to 16*2 loop
         wait until falling_edge(clk);
      end loop;
      enter_pb <= '0';
      for i in 1 to 10*16*2 loop
         wait until falling_edge(clk);
      end loop;

      assert false
         report "Simulation Completed"
         severity failure;

   end process;

end beh;