-- ======================================================================================================
-- ======================================================================================================
library ieee;
use ieee.std_logic_1164.all;

entity pong_top_st is
	port(
	clk, reset: in std_logic;
	btn: in std_logic_vector(1 downto 0);
	hsync, vsync: out std_logic;
	rgb_8bit: out std_logic_vector(23 downto 0);
	vga_pixel_tick: out std_logic;
	blank: out std_logic;
	comp_sync: out std_logic
	);
end pong_top_st;

-- ======================================================================================================
-- ======================================================================================================

architecture arch of pong_top_st is
	signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
	signal video_on: std_logic;
	signal rgb_reg, rgb_next: std_logic_vector(2 downto 0);
	signal rgb: std_logic_vector(2 downto 0);
	signal p_tick: std_logic;

	begin

-- instantiate VGA sync
	vga_sync_unit: entity work.vga_sync
		port map(clk=>clk, reset=>reset,
			hsync=>hsync, vsync=>vsync, comp_sync=>comp_sync,
			video_on=>video_on, p_tick=>p_tick,
			pixel_x=>pixel_x, pixel_y=>pixel_y);

-- instantiate pixel generation circuit
	pong_grf_st_unit: entity work.pong_graph_st(sq_ball_arch)
		port map(clk=>clk, reset=>reset, btn=>btn, video_on=>video_on, 
			pixel_x=>pixel_x, pixel_y=>pixel_y, graph_rgb=>rgb_next);

	vga_pixel_tick <= p_tick;
--	rgb_8bit(0) <= rgb(0);
--	rgb_8bit(1) <= rgb(0);
--	rgb_8bit(2) <= rgb(0);
--	rgb_8bit(3) <= rgb(0);
--	rgb_8bit(4) <= rgb(0);
--	rgb_8bit(5) <= rgb(0);
--	rgb_8bit(6) <= rgb(0);
	rgb_8bit(7) <= rgb(0);
	
--	rgb_8bit(8) <= rgb(1);
--	rgb_8bit(9) <= rgb(1);
--	rgb_8bit(10) <= rgb(1);
--	rgb_8bit(11) <= rgb(1);
--	rgb_8bit(12) <= rgb(1);
--	rgb_8bit(13) <= rgb(1);
--	rgb_8bit(14) <= rgb(1);
	rgb_8bit(15) <= rgb(1);
	
--	rgb_8bit(16) <= rgb(2);
--	rgb_8bit(17) <= rgb(2);
--	rgb_8bit(18) <= rgb(2);
--	rgb_8bit(19) <= rgb(2);
--	rgb_8bit(20) <= rgb(2);
--	rgb_8bit(21) <= rgb(2);
--	rgb_8bit(22) <= rgb(2);
	rgb_8bit(23) <= rgb(2);

-- rgb buffer, graph_rgb is routed to the ouput through
-- an output buffer -- loaded when p_tick = ’1’.
-- This syncs. rgb output with buffered hsync/vsync sig.

	process (clk)
		begin
		if (clk'event and clk = '1') then
			if (p_tick = '1') then
				rgb_reg <= rgb_next;
			end if;
		end if;
	end process;
	rgb <= rgb_reg;

	blank <= video_on; 

end arch;