library ieee;
use ieee.std_logic_1164.all;

entity vga_test is
   port(
      Clk, RESET: in std_logic;
      sw: in std_logic_vector(2 downto 0);
      hsync, vsync: out std_logic;
      vga_b1: out std_logic;
      vga_b2: out std_logic;
      vga_b3: out std_logic;
      vga_b4: out std_logic;
      vga_g1: out std_logic;
      vga_g2: out std_logic;
      vga_g3: out std_logic;
      vga_g4: out std_logic;
      vga_r1: out std_logic;
      vga_r2: out std_logic;
      vga_r3: out std_logic;
      vga_r4: out std_logic
      );
   end vga_test;

architecture arch of vga_test is
   signal rgb_reg: std_logic_vector(2 downto 0);
   signal video_on: std_logic;
      
   begin -- instantiate VGA sync circuit

      vga_sync_unit: entity work.VGA_trials
         port map(clk=>Clk, reset=>RESET, hsync=>hsync,
            vsync=>vsync, 
            video_on=>video_on,
            p_tick=>open, pixel_x=>open,
            pixel_y=>open);

      process(Clk, RESET) -- rgb buffer
         begin
         if (RESET = '1') then
            rgb_reg <= (others => '0');
         elsif (Clk'event and Clk = '1') then
            rgb_reg <= sw;
         end if;
      end process;
      vga_b1 <= rgb_reg(0) when video_on = '1' else '0';
      vga_b2 <= rgb_reg(0) when video_on = '1' else '0';
      vga_b3 <= rgb_reg(0) when video_on = '1' else '0';
      vga_b4 <= rgb_reg(0) when video_on = '1' else '0';
      vga_g1 <= rgb_reg(1) when video_on = '1' else '0';
      vga_g2 <= rgb_reg(1) when video_on = '1' else '0';
      vga_g3 <= rgb_reg(1) when video_on = '1' else '0';
      vga_g4 <= rgb_reg(1) when video_on = '1' else '0';
      vga_r1 <= rgb_reg(2) when video_on = '1' else '0';
      vga_r2 <= rgb_reg(2) when video_on = '1' else '0';
      vga_r3 <= rgb_reg(2) when video_on = '1' else '0';
      vga_r4 <= rgb_reg(2) when video_on = '1' else '0';
   end arch;