This is a very simple exercise in which you will be given a CMOS layout (of an inverter) and you will be required to extract an RC model of the circuit and validate it using the SPICE simulation engine.
You are not required to do the layout since we will likely be transitioning to a commercial CAD system called Cadence. Therefore, I do not want you to learn MAGIC (a layout editor) and later have to learn the layout editor associated with Cadence. You will need to run magic in order to extract an RC model however.
My web page includes a link to the magic layout and SPICE transistor model. Extraction of an RC model involves running magic on the layout (e.g. `magic inverter') and then typing `:extract'. This process generates the file inverter.ext. At the command prompt, run `ext2spice inverter' to create the SPICE file. Using an editor of your choice, e.g. vi, add the SPICE model to the inverter.spice file. You will also have to add some other statements that control the simulation as explained in the documents "Lab 1 Help" and "Magic and Spice Overview".
1) Describe the Simulation Procedure, e.g. how you created the simulation file, what you did to simulate the circuit.
2) Draw the schematic diagram using the magic RC model (inverter.spice).
3) Plot the circuit by writing the cif file (from magic, issue :cif write filename) and then run `pplot -C -o filename.ps filename.cif' from the UNIX prompt.
4) Report the input rise and fall times.
5) What is the output load capacitance ?
6) Measure and report the output rise and fall times.