Instructor:
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Professor Jim Plusquellic
Text:
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Principles of CMOS VLSI Design: A Systems Perspective,
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by Neil H.E. Weste and Kamran Eshraghian.
Supplementary texts:
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Digital Integrated Circuit Design, by Ken Martin, Oxford University Press (2000).
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Digital Integrated Circuits, A Design Perspective
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by Jan M. Rabaey, Prentice Hall (1996).
Further Info:
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http://www.cs.umbc.edu/~plusquel/
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To introduce the concepts and techniques of modern integrated circuit design and testing (CMOS VLSI).
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To provide experience designing integrated circuits using Commercial Computer Aided Design (CAD) Tools (CADENCE).
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The Design Process
: An iterative process that refines an "idea" to a manufacturable device through at least five levels of design abstraction.
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Abstraction
: A very effective means of dealing with design complexity.
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Creating a model at a higher level of abstraction involves replacing detail at the lower level with simplifications.
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Simulation
: The functional behavior of the design (or a parameter such as power) is determined by applying a set of excitation vectors to a circuit model.
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TTL (Transistor-Transistor logic).
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First successful IC logic family.
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Composed largest fraction of digital IC market until 80's.
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Power consumption
per gate set upper limit on integration density.
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I
2
L (Integrated Injection Logic):
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An attempt to provide a high integration density, low power bipolar family of logic.
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MOS (Metal-Oxide-Silicon): Actually, we use polysilicon for gates now.
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Gate stability problems solved in 60's.
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CMOS was first !
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Complexity of manufacturing process delayed use until 80's.
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PMOS-only used through early 70's.
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In 1974, the 8080 microprocessor was implemented using faster NMOS-only.
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Late 70's, NMOS-only started suffering from same problem as high density bipolar technology --
power consumption
.
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Since early 80's, CMOS remains the technology of choice.
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However,
power consumption
is now becoming a problem.
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And there is no new technology around the corner to alleviate the problem.
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When performance is the main issue, other technologies are used:
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BiCMOS: High speed memory and gate arrays.
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ECL (Emitter-coupled logic): Even higher performance.
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Galium-Arsenide
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Silicon-Germanium
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Superconducting Technologies
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Moore's Law: Integration density doubles every 18 months.
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We'll see more on this later.
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For example, Microprocessors:
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The million transistor/chip barrier crossed in `88 with the 486.
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Impact of this revolution on design:
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Hand crafting not possible anymore (as was done for the 4004).
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Hierarchy
is used in the design of the Pentium.
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The processor is a collection of modules each composed of cells.
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Re-use of cells reduces design effort and increases the chance of a first-time right implementation.
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The use of hierarchy is a key ingredient to the success of the digital circuit.
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Reason why large analog designs never caught on.
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Abstraction
is also possible in digital designs.
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And difficult to apply effectively to analog designs.
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Critical element in dealing with complexity.
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A multiplier, for example, can be designed and treated like a black box.
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The performance of the multiplier is only marginally influenced by the way it is used in a larger system.
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This divide and conquer (
hierarchical
) approach allows the designer to deal with a much smaller number of well characterized modules (or
abstractions
).
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Abstraction levels:
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Physical level
: Rectangles, design rules.
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Circuit level
: Transistors, R and C, analog voltage/current values.
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Switch level: Transistors, R and C, multi-valued logic.
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Logic level
: Boolean logic gates, binary valued logic.
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Register Transfer Level
: Adders, datapaths, binary valued words.
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Functional level
: Processors, programs and data structures.
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Entire CAD design frameworks are based on this design philosophy.
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These have made it possible to achieve current design complexity.
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Design tools include:
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Simulation at various complexity levels.
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Design verification.
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Layout generation.
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Design synthesis.
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Standard cells are a popular design style that makes layout generation easy.
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Layouts of basic gates such as AND, OR, NAND, NOR, and NOT as well as arithmetic and memory modules are provided as input.
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These cells are designed with similar characteristics, such as constant height, and can be manipulated easily to generate a layout.
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If design automation solves all the problems, why be concerned with digital circuit design?
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Reality is more complex and a knowledge of digital circuit design will be important for some time to come.
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Someone has to design and implement the module libraries.
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Porting from technology generation to technology generation (different feature sizes) is NOT automatic.
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This occurs approximately every two years !
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Creating an adequate
model
of a cell/module requires an in-depth understanding of its internal operation.
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A significant part of digital circuit design focuses on analysis of internal circuit operation.
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The library-based approach does NOT work for all situations, i.e. high performance designs like microprocessors.
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For Application Specific Integrated Circuits (
ASICs
), library-based approach works well since the design constraints (speed, power, cost and area) are reduced.
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For microprocessor design, which push technology to its limits, this approach becomes less attractive.
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The abstraction-based approach is only correct to a certain degree.
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Performance of a module, i.e. an adder, is substantially influenced by the way it is connected in its environment (
interconnect parasitics
).
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Scaling tends to emphasize other deficiencies of the abstraction-based approach.
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Global entities, such as clock signals and supply lines, are significantly affected by scaling.
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Clock distribution, circuit synchronization and supply-voltage distribution are becoming more and more critical.
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New design issues emerge over time.
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Power dissipation issue periodically re-emerges.
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Recently, the ratio between device and interconnect parasitics (and consequently the appropriate delay model) is changing.
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Trouble shooting an erroneous design requires circuit expertise.
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A process applied to hardware devices whose goal is to determine if the device is free of fabrication defects that would otherwise cause the device to violate its
functional
or
parametric
specifications.
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Determines if the device is functional (meets the truth table specification).
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It is applied to every device and therefore needs to be simple and fast.
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For logic test, we are done as soon as we observe the first error.
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However, we may be interested in locating the fault as well, for chip or process debug.
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The objective of
diagnosis
is to determine the location of the fault.
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Based on the analysis of a
continuous
circuit parameter, in contrast to functional test which analyzes
logic signals
.
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My own research focuses on a parametric testing method called
Transient Signal Analysis
(TSA).
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Check a number of
continuous
circuit variables such as noise margins, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior.
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These parameters are usually checked under a number of different temperatures and supply voltages.
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Note that the stimulus is digital, but the analysis of the output is performed on an
analog
value or waveform.
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When Device Under Test (DUT) is digital logic device, the stimuli are called
test patterns
or
test vectors
.
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A device test consists of applying the test patterns one at a time (by a tester) to the Primary Inputs of the DUT.
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The test patterns are defined in a
test program
that describes the waveforms to be applied, the voltage levels and the clock frequency.
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A new part is automatically fed to the tester and a probe card or DUT board is used to connect the inputs and outputs of the tester to the pins of the die or package.
