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Need simple models to estimate system performance in terms of signal delay and power dissipation.
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Issues include:
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Resistance, capacitance and inductance calculations.
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Delay estimations.
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Determination of conductor size for power and clock distribution.
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Power consumption.
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Charge sharing mechanisms.
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Design Margining.
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Reliability.
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Effects of scaling.
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The resistance of a uniform slab of conducting material may be expressed as
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For example, in a layout editor, such as magic or virtuoso:
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Channel resistance can be estimated in the
linear
region as:
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A range of 1,000 to 30,000 ohms/square are possible for n-channel and p-channel devices.
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Typical betas for identically sized devices; n-dev: ~90, p-dev: ~30 microA/V
2
.
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Temperature changes both mu (mobility) and V
t
(threshold voltage) and, therefore channel resistance.
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Channel resistance increases with temperature, approximately +0.25% per degree C above 25 degrees.
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Metal and poly resistance change about 0.3% and well diffusions about 1% per degree C.
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Switching speed of MOS systems
strongly
dependent:
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Parasitic capacitances associated with the MOS transistor.
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Interconnect capacitance of "wires".
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Resistance of transistors and wires.
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Total
load
capacitance on the output of a CMOS gate is sum of:
-
Gate capacitance (of
receiver
logic gates downstream).
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Driver
diffusion (source/drain) capacitance.
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Routing (
line
) capacitance of substrate and other wires.
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Let's consider approximations of each of these capacitances and subsequent approximations of delay based on these expressions.
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The capacitance of a MOS transistor can be modeled using 5 capacitors.
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An approximation of gate capacitance (C
gs
, C
gd
and C
gb
) is given as:
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For example, for thin-oxide thickness of 15 nm,
-
This is a conservative estimate of gate capacitance that does not include fringing fields (extrinsic) gate capacitance.
-
Gate capacitance increases as the thin-oxide thins.
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An approximation (
lumped model
) of source/drain capacitance (C
sb
and C
db
) is given as:
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This model assumes a zero DC bias across the junction.
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Because of fan-out,
gate
capacitance usually dominates the loading.
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Routing capacitance between metal and poly can be approximated using a parallel-plate model.
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The effect of the fringing fields is to increase the effective area of the plates.
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Appropriate if the wire delay is MUCH less than the gate delay, e.g.,
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This expression derives from the expression for RC delay (we'll see this later).
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As an example, assuming gate delay is 200ps, what is the maximum length of a minimal-width metal wire (in 1.0um technology) that we can use without worrying about the RC delay of the wire itself?
-
Assume Metal1 = 0.05 Ohms/square and 30 aF/um
2
.
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But this assumes there is no gate load capacitance.
-
A conservative estimate is 5000 lambda (~16,330/3).
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In a 1.0um process, RC delay MUST be considered for any wire > 2.5mm.
-
But for now, let's consider "electrical nodes" for which we can ignore distributed RC effects.
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Our model and definitions:
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Fall/rise time, e.g. t
f
, computed between 10% and 90% of V
DD.
-
Propagation delay, t
dr
, computed at 50% points on input and output waveforms.
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How do we model gate delay?
-
Assume input is driven by a step waveform (unlike previous slide).
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Approximation for fall time:
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Note that the input waveform's finite slope will also effect this result -- adding a small amount of additional delay which is ignored here -- see text for details.
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For example, let's compute the delay between G
D
and G
R
:
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If the wire delay ~= gate delay, then we will have to use a different approximation consisting of three components:
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A wire can be represented in terms of several RC sections:
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A discrete analysis of this circuit yields an approximate delay of:
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As n becomes large (and the sections becomes small), this reduces to:
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RC effect dominates for very long wires due to l
2
term, e.g., doubling the length of the wire, quadruples the delay.
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For example, consider a long poly wire:
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The buffer is one possible method of reducing the propagation delay.
-
Assume r = 20 Ohms/micron and c = 0.4 fF/micron, then:
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The buffer version is faster if its delay is less then 8ns. This is easily achieved.
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When are distributed RC effects important to consider:
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Long wires with high resistance, e.g. poly wires.
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Long, heavily loaded clock lines.
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An example showing that reducing R at the expense of C helps a lot in some cases:
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Assume clock wire runs over 20mm and 50pF is distributed evenly along the line.
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Assume r = 0.05 Ohms/um.
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Then clock skew (delay to the end of the wire) is:
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Solutions include adding a buffer, distributing the clock from the top center and/or widening the metal wire.
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For example, reducing l to 10mm and widening the clock wire to 20um:
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How does the distributed RC model differ from lumped model?
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Note that these effects are completely ignored in the simple gate delay model.
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FYI: We estimate delay using RC time constants assuming that the time taken for a signal to reach 62.3% of its final value approximates the switching point of an inverter.
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Construct an equivalent inverter, e.g.,
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3-input NANDs are closely balanced since n beta is about 3 times larger than p beta.
