BitGen

BitGen is a program for converting digital bitstreams to analog voltage sources suitable for circuit simulation in programs such as SPICE and Spectre.

BitGen is written in Perl and uses the Perl interface to Tk, Perl/Tk. To run BitGen, you need the following installed:

Once these are installed, simply change the first line of bitgen.pl to point to your Perl executable, and you're set. You can run it from a shell prompt, or, if you've installed the NCSU CDK for use with Cadence, from the ``Setup -> Stimulus -> Run BitGen...'' menu entry in Analog Artist (see the file local/menus/simui.menus).

BitGen is included in the NCSU Cadence Design Kit.

Please email your comments, suggestions, bug reports and patches. (Also, write if only to say you like the program! A little encouragement goes a long way!)

Everyone likes screenshots...

The main BitGen window, before any sources have been defined:

The BitGen window after reading in a file containing three voltage sources and in the process of selecting ``SPICE'' as the netlist format:

The voltage sources are shown in the ``source list'' window, from which you can quickly find the source you're looking for:

The following output is produced when you click ``Export'':

* input data
Vinput input 0 pwl(0 0
+ 2.000000e-08 0.00 2.050000e-08 3.30 3.000000e-08 3.30 3.050000e-08 0.00 
+ 4.000000e-08 0.00 4.050000e-08 3.30 5.000000e-08 3.30 5.050000e-08 0.00 
+ 7.000000e-08 0.00 7.050000e-08 3.30 9.000000e-08 3.30 9.050000e-08 0.00 
+ 1.000000e-07 0.00 1.005000e-07 3.30 1.100000e-07 3.30 1.105000e-07 0.00 
+ 1.200000e-07 0.00 1.205000e-07 3.30 1.400000e-07 3.30 1.405000e-07 0.00 
+ 1.500000e-07 0.00 1.505000e-07 3.30 1.600000e-07 3.30 1.605000e-07 0.00 
+ 1.700000e-07 0.00 1.705000e-07 3.30 1.900000e-07 3.30 1.905000e-07 0.00 
+ 2.000000e-07 0.00 2.005000e-07 3.30 2.100000e-07 3.30 2.105000e-07 0.00 
+ 2.200000e-07 0.00 2.205000e-07 3.30 2.400000e-07 3.30 2.405000e-07 0.00 
+ 2.500000e-07 0.00 2.505000e-07 3.30 2.600000e-07 3.30 2.605000e-07 0.00 
+ 2.700000e-07 0.00 2.705000e-07 3.30 2.900000e-07 3.30 2.905000e-07 0.00 
+ 3.000000e-07 0.00 3.005000e-07 3.30 3.100000e-07 3.30 3.105000e-07 0.00 
+ 3.400000e-07 0.00 3.405000e-07 3.30 3.500000e-07 3.30 3.505000e-07 0.00 
+ 3.700000e-07 0.00 3.705000e-07 3.30 3.900000e-07 3.30 3.905000e-07 0.00 
+ 4.000000e-07 0.00 4.005000e-07 3.30 4.100000e-07 3.30 4.105000e-07 0.00 
+ 4.200000e-07 0.00 4.205000e-07 3.30 4.400000e-07 3.30 4.405000e-07 0.00 
+ 4.500000e-07 0.00 4.505000e-07 3.30 4.600000e-07 3.30 4.605000e-07 0.00 
+ 4.700000e-07 0.00 4.705000e-07 3.30 4.900000e-07 3.30 4.905000e-07 0.00 
+ 5.000000e-07 0.00 5.005000e-07 3.30 5.100000e-07 3.30 5.105000e-07 0.00 
+ 5.200000e-07 0.00 5.205000e-07 3.30 5.400000e-07 3.30 5.405000e-07 0.00 
+ 5.500000e-07 0.00 5.505000e-07 3.30 5.600000e-07 3.30 5.605000e-07 0.00 
+ 5.700000e-07 0.00 5.705000e-07 3.30 5.900000e-07 3.30 5.905000e-07 0.00 
+ 6.000000e-07 0.00 6.005000e-07 3.30 6.100000e-07 3.30 6.105000e-07 0.00 
+ 6.400000e-07 0.00 6.405000e-07 3.30 6.500000e-07 3.30 6.505000e-07 0.00 
+ 6.700000e-07 0.00 6.705000e-07 3.30 6.900000e-07 3.30 6.905000e-07 0.00 
+ 7.000000e-07 0.00 7.005000e-07 3.30 7.100000e-07 3.30 7.105000e-07 0.00 
+ 7.200000e-07 0.00 7.205000e-07 3.30 7.400000e-07 3.30 7.405000e-07 0.00 
+ 7.500000e-07 0.00 7.505000e-07 3.30 7.600000e-07 3.30 7.605000e-07 0.00 
+ 7.700000e-07 0.00 7.705000e-07 3.30 7.900000e-07 3.30 7.905000e-07 0.00 
+ 8.000000e-07 0.00 8.005000e-07 3.30 8.100000e-07 3.30 8.105000e-07 0.00 
+ 8.200000e-07 0.00 8.205000e-07 3.30 8.400000e-07 3.30 8.405000e-07 0.00 
+ 8.500000e-07 0.00 8.505000e-07 3.30 8.600000e-07 3.30 8.605000e-07 0.00 
+ 8.700000e-07 0.00 8.705000e-07 3.30 8.900000e-07 3.30 8.905000e-07 0.00 
+ 9.000000e-07 0.00 9.005000e-07 3.30 9.100000e-07 3.30 9.105000e-07 0.00 
+ 9.300000e-07 0.00 9.305000e-07 3.30 9.600000e-07 3.30 9.605000e-07 0.00 
+ 9.900000e-07 0.00)
* 8-bit control vector
Vcontrol0 control0 0 pwl(0 3.3
+ 1.000000e-08 3.30 1.100000e-08 0.00 2.000000e-08 0.00 2.100000e-08 3.30 
+ 3.000000e-08 3.30)
Vcontrol1 control1 0 pwl(0 3.3
+ 3.000000e-08 3.30)
Vcontrol2 control2 0 pwl(0 0
+ 2.000000e-08 0.00 2.100000e-08 3.30 3.000000e-08 3.30)
Vcontrol3 control3 0 pwl(0 0
+ 1.000000e-08 0.00 1.100000e-08 3.30 3.000000e-08 3.30)
Vcontrol4 control4 0 pwl(0 3.3
+ 3.000000e-08 3.30)
Vcontrol5 control5 0 pwl(0 3.3
+ 1.000000e-08 3.30 1.100000e-08 0.00 2.000000e-08 0.00 2.100000e-08 3.30 
+ 3.000000e-08 3.30)
Vcontrol6 control6 0 pwl(0 3.3
+ 1.000000e-08 3.30 1.100000e-08 0.00 2.000000e-08 0.00 2.100000e-08 3.30 
+ 3.000000e-08 3.30)
Vcontrol7 control7 0 pwl(0 0
+ 1.000000e-08 0.00 1.100000e-08 3.30 3.000000e-08 3.30)
* system clock
Vclk clk 0 pulse(0 3.3 0 2e-09 2e-09 8e-09 2e-08 )
Changelog

From the Help:

The author welcomes any suggestions, comments, or questions.

Copyright (c) 1999, 2000 Toby Schaffer. All rights reserved. This program is free software; you can redistribute it and/or modify it under the same terms as Perl itself.

IN NO EVENT SHALL THE AUTHOR OR DISTRIBUTORS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE, ITS DOCUMENTATION, OR ANY DERIVATIVES THEREOF, EVEN IF THE AUTHOR HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

THE AUTHOR AND DISTRIBUTORS SPECIFICALLY DISCLAIM ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, AND THE AUTHOR AND DISTRIBUTORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.