Parameterized Cells

Parameterized cells (pcells) are basically layout macros; when the you instantiate a pcell you fill in various parameters, and the layout of the instance changes to reflect these values. Where you get the pcells from depends on the type of design library you have:

• If your library was created with the ``Attach to existing tech file'' option, get pcells from the technology library to which your library is attached by entering its name in the ``Create Instance'' form. The technology libraries that come with the CDK have names similar to NCSU_TechLib_tsmc03.
• If your library was created with the ``Compile tech file'' option (i.e., your design library is its own technology library), the pcells are in your design library in a category called layout_macros, and these should be used.

As of now, the following pcells are defined:

• Contacts:

       ntap        Nwell ohmic 
       ptap        Psubstrate ohmic 
       m1_n        metal1 - N-diffusion 
       m1_p        metal1 - P-diffusion 
       m1_poly     metal1 - poly 
       m1_elec     metal1 - elec (poly 2) 
       m2_m1       metal2 - metal1 
       m3_m2       metal3 - metal2 
       m4_m3       metal4 - metal3 
       m5_m4       metal5 - metal4 
       m6_m5       metal6 - metal5 
      

• Capacitors:

       cap         thin-oxide (linear) capacitor
      

• Devices:

       nmos        N-mosfet
       pmos        P-mosfet
       nmos_hv     high-voltage N-mosfet
       pmos_hv     high-voltage P-mosfet
      

When compiling a technology library, all pcells whose required layers exist in that technology are created.

Contacts are parameterized by row and column. Contacts are placed with minimum spacing.

The thin-ox capacitor is parameterized by total capacitance desired, height and width. The user can also specify the number of rows of contacts to the active and poly capacitor plates.

For the transistors, the user specifies both width and length (which are subject to being on a half-lambda grid, and also to minimum values). Additionally, the user can optionally define one of two cases:

1. multiple devices in parallel (i.e., with a column of contacts between devices) by setting the m (for ``multiplier'') parameter
2. multiple devices in series by setting the fingers parameter (adjacent devices have minimum spacing)

The two are mutually exclusive.

The pcell SKILL code is in local/skill/pcells.

Path stitching

Path stitching is a quick way to change from one layer to another when running wires. When creating a path (hit p or choose the ``Create->Path...'' menu entry) with any metal or poly layer, the user can automatically change to any other wiring layer physically adjacent to the current layer. For example, when running a metal 2 path in a three-metal process, the user can change to either metal 1 or metal 3, and Virtuoso will automatically place the correct contact type and change the wiring layer. (This is almost identical to Magic's ``path tool.'') The CDK includes the required symbolic contact definitions, which are located in the technology libraries.

Virtuoso-XL