-
Magnitude Comparators
:
-
May be built from an adder, complementer (XOR gates) and a zero detect unit.
-
Think about the modifications necessary to make it a signed comparator (Hint: A couple of XOR gates).
-
Asynchronous: Based on the Toggle register.
-
Not a good choice for performance and testability (with no reset).
-
Replace AND gate with an adder for up/down counting capability.
-
Weste and Eshraghian also show a version that can be initialized.
-
Multiplication can be broken down into two steps:
-
Computation of partial products.
-
Accumulation of the shifted partial products.
-
Multipliers may be classified by the format in which data words are accessed:
-
Serial
-
Serial/parallel
-
Parallel
-
The parallel form computes the partial products in parallel.
-
Parallel Unsigned Multiplication:
-
Parallel Multiplication:
-
Multiplication is carried out using a bitwise AND of the operands, X
i
and Y
i
.
-
Most of the work (and delay) is in summing the partial products.
-
From the delay expression and the fact that all critical paths have the same length, minimizing t
mult
requires minimizing both t
carry
and t
sum
.
-
This is in contrast with the adder where minimizing t
carry
was key.
-
The transmission gate adder is a good choice here.
-
Parallel Signed Multiplication:
-
Parallel Signed Multiplication:
-
Carry-Save Multiplier:
-
Carry bits can be passed diagonally downwards instead of to the left.
-
Here the carry bits are not immediately added but rather "saved" for the next adder stage.
-
Serial Unsigned Multiplication:
-
Serial/Parallel Unsigned Multiplier shown in Weste and Eshraghian.
-
Booth Encoding:
-
A special encoding of the multiplier word reduces the number of required addition stages and speeds up multiplication substantially.
-
The number of partial products (and additions) is halved, resulting in area and speed advantage.
-
The disadvantage is a somewhat more involved multiplier cell.
-
AND operation replaced with inversion and shift logic.
-
Virtually every multiplier in use employs the Booth scheme.
-
Wallace Multiplier:
-
Trees can be used to replace the linear partial-sum adders:
-
Right/Left 1-bit shifter:
