-
One method to reduce the circuit complexity of static CMOS.
-
Here, the logic function is built in the PDN and used in combination with a simple load device.
-
Let's assume the load can be represented as
linearized resistors
.
-
When the PDN is on, the output voltage is determined by:
-
This logic style is called
ratioed
because care must be taken in scaling the impedances properly.
-
Note that full complementary CMOS is
ratioless
, since the output signals do not depend on the size of the transistors.
-
In order to keep the noise margins high, R
L
>> R
PDN
.
-
However, R
L
must be able to provide as much current as possible to minimize delay.
-
These are
conflicting
requirements:
-
R
L
large: Noise margins.
-
R
L
small: performance and power dissipation.
-
This has resulted in a wide variety of possible load configurations.
-
Simple resistor
-
Available charge current as a function of the output voltage is linear:
-
Disadv: Charge current drops rapidly once V
out
starts to rise.
-
Current source
-
Ideal
in the sense that the available current is independent of the output voltage.
-
It is easy to prove that t
pLH
is reduced by 25% over the resistor load.
-
Depletion load
-
The depletion load gate shown previously emerged as the
most popular
gate in the NMOS era (up until the early 80s).
-
The load is an NMOS depletion mode transistor (
negative threshold device
) with the gate connected to the output (source).
-
Note that the device is on when V
GS
= 0.
-
The load acts as a
current source
(first-order), given by its saturation equation:
-
Depletion load (cont)
-
The load line
deviates
from the ideal current source for two reasons:
-
(a) The
channel length modulation
factor modulates current in saturation mode.
-
(b) The source of the load transistor is connected to the output of the inverter.
-
The
body effect
causes the threshold of the load transistor to vary as a function of V
out
.
-
The body effect reduces |V
Tn
| and the available current for increasing values of V
out
.
-
Nevertheless, the depletion load out-performs the resistive load and requires less area!
-
For example, implementing a 40K Ohm resistor takes 3,200 um
2
when implemented using n
+
-diffusion.
-
Pseudo-NMOS
-
A
grounded PMOS
device presents an even better load.
-
It is better than depletion NMOS because there is
no body effect
(its V
SB
is constant and equal to 0).
-
Also, the PMOS device is driven by a V
GS
= -V
DD
, resulting in a higher load-current level than a similarly sized depletion-NMOS device.
-
(ignoring channel length modulation)
-
The V
OH
(=V
DD
) from the dc transfer characteristic is the same as that for the full complementary device.
-
V
OL
differs from GND, however.
-
Pseudo-NMOS (cont)
-
V
OL
can be obtained by equating the currents through the driver and load devices for V
in
= V
DD
.
-
Here, the
NMOS
driver resides in
linear mode
while the
PMOS
load is in
saturation
:
-
Assuming V
Tn
= |V
Tp
|, solving for V
OL
yields:
-
For example, if k
p
= k
n
, V
OL
= V
DD
- V
T
, which is clearly unacceptable.
-
For r = k
p
/k
n
= 1/4, V
OL
= (5 - 0.8)*0.134 ~= 0.56V.
-
Pseudo-NMOS (cont)
-
Similarly, V
M
can be computed by setting V
in
= V
out
and solving the current equations
-
This assumes the NMOS and PMOS are in
saturation
and
linear
, respectively.
-
Design challenges:
-
This clearly indicates that V
M
is
not
located in the middle of the voltage swing (e.g. if they are equal, the square root yields 0.707).
-
The rise and fall times are
asymmetrical
.
-
This gate consumes
static power
when the output is low.
-
Pseudo-NMOS (cont)
-
Let's assume the load can be approximated as a
current source
for the entire operation region.
-
Trade-offs:
-
To reduce static power, I
L
should be low
.
-
To obtain a reasonable NM
L
, V
OL
= I
L
R
PDN
should be low
.
-
To reduce t
pLH
~= (C
L
V
DD
)/(2I
L
), I
L
should be high
.
-
To reduce t
pHL
~= 0.69R
PDN
C
L
, R
PDN
should be kept
small
.
-
Pseudo-NMOS (cont)
-
The r = (W/L)
n
/(W/L)
p
in the expression for V
OL
defines NM
L
.
-
For example, to obtain a V
OL
of 0.2V (1.2 um tech., V
DD
=5V) requires a ratio of r=3. This also guarantees the 4th condition.
-
However, 1 and 3
are contradictory
: realizing a faster gate (t
pLH
) means more static power consumption and reduced noise margin.
-
Pseudo-NMOS attractive for complex gates with large fan-in.
-
A minimum sized gate consumes 1mW !
-
Even better loads
-
Consider the following modification to the pseudo-NMOS NOR.
-
Here, it is known that the inputs switch only during certain time periods.
-
For example, an address decoder which should only switch when the address changes.
-
In stand-by mode, low power consumption and large noise margins.
-
For address change, high power fast t
pLH
transition.
-
Even better loads (cont)
-
It's possible to
completely eliminate
static current:
-
Differential Cascade Voltage Switch Logic
(DCVSL).
-
PDN
1
and PDN
2
are complementary.
-
Assume PDN
1
conducts, input to M
2
is turned on, pulling up
Out.
-
This in turn, shuts off M
1
.
-
Speed advantage
of pseudo-NMOS (reduced output parasitics) with
no static power consumption
, but occupies
extra area
.
-
Even better loads (cont)
-
However, transistors can be shared between PDN
1
and PDN
2
.
-
This gate has been used to implement fast error-correcting logic in memories.
-
Plus, the availability of complementary signals eliminate extra inverter stages.
