-
Dynamic logic reduces the fan-in, similar to pseudo-NMOS,
without
the static power consumption.
-
Precharge
:
-
When
f
=0, the output node
Out
is precharged to V
DD
by M
p
.
-
Evaluation
:
-
When
f
=1, M
e
is on and node
Out
discharges conditionally, depending on the value of the input signals.
-
If no path exists during evaluate, then
Out
remains high via C
L
(diffusion, wiring and gate capacitance).
-
Note that once
Out
is discharged, it cannot be recharged.
-
Therefore, the inputs can make
at most
one transition
during evaluation.
-
Properties:
-
The logic function is implemented in the NMOS pull-down network.
-
The # of transistors is
N+2
instead of 2N
-
It is non-ratioed (noise margin does not depend on transistor ratios).
-
It only consumes dynamic power.
-
Faster switching due to reduced internal and downsteam capacitance.
-
Steady-state behavior
:
-
V
OL
and V
OH
are GND and V
DD
.
-
Our standard definitions of noise margins and switching thresholds
do not include time
, which is required in this case.
-
Steady-state behavior (cont):
-
For example, noise margins depend on the length of the evaluate.
-
If
clk
is too long, leakage affects the high output level significantly.
-
Since the pull down network starts to conduct when the input signal exceeds V
Tn
, it is reasonable to set V
M
, V
IH
, V
IL
= V
Tn
.
-
Therefore, NM
L
is very low.
-
Note that this is a conservative estimate since
subthreshold leakage
occurs for inputs below V
Tn
.
-
Also note that the high output level is sensitive to noise and coupling disturbances because of its
high
output impedance.
-
The high value of NM
H
compensates for this increased sensitivity.
-
Dynamic behavior:
-
Also, after precharge, the output is high. Therefore, t
pLH
= 0!
-
This is somewhat unfair since it ignores the precharge time.
-
The designer is free to choose the size of the PMOS device, smaller is faster but increases load and t
pHL
.
-
The t
pHL
is proportional to C
L
and current-sinking capabilities of PDN.
-
M
e
slows down the gate a little.
-
There are three sources of noise:
-
Charge Leakage
-
Sets the minimum clock to 250Hz to 1kHz (testing difficulties)
-
Charge Sharing
-
One way to combat both of these:
-
Pseudo-static
: M
bl
is a highly resistive (long and narrow) PMOS transistor.
-
Alternatively,
precharge
internal nodes using a clock driven PMOS.
-
Clock Feedthrough
-
The clock is coupled to the storage node via C
gs
and gate-overlap caps.
-
May forward bias the junction and inject electrons into substrate.
-
Fix is to restrict the inputs to making only a
0->1
transition during eval.
-
During evaluation, either the output of the first DOMINO stays at 0 (no delay!) or makes a
0->1
transition.
-
The transition may ripple all the way down the chain.
-
Properties:
-
Only
non-inverting
logic can be implemented.
-
Appropriate for complex, large fan-out circuits such as ALUs or control circuits.
-
Very high speeds can be achieved, t
pHL
= 0.
-
In the past, DOMINO was used in the design of a number of high speed ICs.
-
The first 32-bit microprocessor (BellMAC 32) used it.
-
Recently, pure DOMINO circuits are rare, mainly due to the non-inverting logic property.
-
PUN
networks replace the static inverters.
-
Note that the
f
p blocks are driven with the
Clk_bar
so that the precharge and evaluate periods coincide.
-
np-CMOS
logic style is
20%
faster than DOMINO, despite the slower PMOS pull-up devices.
-
The DEC alpha-processor (first at 250MHz) used this logic extensively.
-
Disadv: NM
L
= V
Tn
and NM
H
= |V
Tp
|.
-
We've already discussed sources of power consumption in CMOS inverter.
-
We now discuss the effects of
switching activity
,
glitching
and
direct-path
current.
-
Note that the factor
f
0->1
complicates the analysis for complex gates.
-
Factors affecting the
switching activity
include the
statistics of the input signals
, the
circuit style
(dynamic/static),
the function
, and
network topology
.
-
These are incorporated by:
-
where
f
is the average event rate, and P
0->1
is the
probability
an input transition results in a
0->1
power-consuming event.
-
Consider a
2-input
NOR gate, assume the input signals have a uniform distribution of high and low values.
-
e.g., the 4 input combinations,
AB
=
00
,
01
,
10
,
11
, are equally likely.
-
Therefore, the probability the output is low or high is
3/4
and
1/4
, respectively.
-
The probability of an energy consuming transition is the probability that the output is initially low, 3/4, times the probability it will become high, 1/4.
-
Note that the output probabilities are
no longer uniform
.
-
This suggests that the input signals are not uniform, since gates are typically cascaded.
-
The probability that the output is 1 (P
1
) is a function of the
input distributions
, P
A
and P
B
(the probabilities the inputs are 1).
-
The transition probability is then:
-
Derive these expressions for AND, OR and XOR.
-
With no reconvergent fan-out, the probability that
X
undergoes a power consuming transistion is
3/16
.
-
X
=
1
, 3 out of 4 times. Therefore,
X
has an uneven distribution yielding a transition probability on
Z
as:
-
The orderly calculations from input to output is not possible for
-
Circuits with
feedback
(sequential circuits).
-
Circuits with
reconvergent fanout
.
-
In the latter case, the input signals are
not
independent.
-
The procedure above yeilds
15/64
for the transition probability.
-
However, reduction yields
Z
=
B
, and the P
0->1
transition probability on
Z
is (1/2 X 1/2) = 1/4.
-
Conditional probabilities
take signal inter-dependencies into account.
-
For example,
Z
=
1
iff
B
and
X
=
1
.
-
This expresses the probability that
B
and
X
are
1
simultaneously.
-
If a dependency exists, a
conditional probability
is required for expansion:
-
What about
dynamic circuits
?
-
During precharge, the output node is charged to 1.
-
Therefore, power is consumed every time the PDN is on (output is 0), independent of the preceding or following values!
-
Power consumption is determined solely by signal value probabilities, and
not
by transition probabilities.
-
These is always
larger
than the transition probability, since the latter is the product of two signal probabilities both of which is smaller than 1.
-
For example, the
0-probability
of a
2-input
NOR is
-
If the inputs are equally probably, there is a 75% chance of a
1->0
.
-
Note C
L
is smaller than a static gate but the clock load must be considered.
-
The finite propagation delay through gates in a network can cause spurious transitions called
glitches
,
critical races
or
dynamic hazards
.
-
These are multiple transitions during a single clock cycle.
-
Assume a unit delay and all inputs arrive at the same time.
-
The second NOR evaluates
twice
, the first one with the previous value of
X
. This consumes unnecessary power.
-
Redesign can eliminate glitches by matching delays along signal paths.
-
Crowbar currents occur when both NMOS and PMOS are on simultaneously.
-
As is true for glitches, these do
not
occur in dynamic circuits.
-
The power dissipated is a function of the
on-time
of the transistors and their
operation mode
.
-
For large C
L
(left), V
DS
for the PMOS remains at
0
during entire input transition. I
SC
is approximately
0
in this case.
-
For small C
L
(right), V
DS
is V
DD
and is maximal (saturation).
-
Neither case is acceptable. Actually,
matching
rise/fall times is optimal.
-
Assuming short-circuit current, glitching and leakage can be kept in bounds, the dominant power consumption is
dynamic power
.
-
Power can be reduced by manipulating V
DD
and C
eff
, (C
L
* P
0->1
).
-
Reducing V
DD
is a big win because of the
quadratic
dependence.
-
Although
PDP
decreases for lower V
DD
, delay
increases
, as predicted by.
-
Delay increases substantially for V
DD
close to 2*V
T
.
-
Therefore, to conserve energy, we should operate at the
slowest
possible speed.
-
To maintain throughput (compensate for increased delays), one approach is to
lower
threshold voltages.
-
As we've seen, lowering threshold voltage, increases
subthreshold leakage
.
-
This raises the minimum clock frequency (dynamic circuits).
-
This increases standby currents and reduces noise margins (static circuits).
-
Note that the concept of zero leakage is preconceived.
-
For example, the following configurations yield the same performance in a 0.25 um CMOS process.
-
V
DD
= 3V, V
T
= 0.7V
-
V
DD
= 0.45V, V
T
= 0.1V
-
However, the power consumption is reduced in the latter by
45X
!
-
For dynamic circuits, the power savings is only about a factor of 8.
-
Architectural (
area for power
) compensations are also possible.
-
When power supply voltage is lower bound due of external constraints or performance, the only other means is to reduce C
eff
.
-
This is achieved by reducing both the
physical cap
. and
switching activity
.
-
Lowering the physical cap. usually improves performance as well.
-
For example, a CPL adder reportedly uses 30% less power (at 4V) compared with a static version.
-
Since most cap. is due to
transistor cap.
(diffusion and gate), this suggests the use of minimum sized devices whenever possible.
-
Larger is only justified for large fan-outs and wiring capacitances.
-
Note this contradicts the standard cell philosophy which use larger transistors in order to accommodate a wider ranges of loads.
-
Reducing switching activity can be accomplished by
point-to-point buses
and
re-ordering inputs
to gates (see text for examples).
-
Choosing a logic style depends on Ease of design, Robustness, System clocking requirements, Fan-out, Functionality and Testing.
-
Static is robust and easy to design (ameanable to design automation).
-
Complementary complex gates are expensive in area and performance.
-
Pseudo-NMOS is simple and fast but reduces noise margins and increases power consumption.
-
Pass-transistor logic is good for certain classes of circuits (MUX/adders).
-
Dynamic logic gives fast and small circuits but complicates the design process and restricts the minimum clock rate.
-
For a
4-input
NAND gate:
|
Style
|
Ratioed
|
Static power
|
# of trans.
|
Area (um2)
|
delay (ns)
|
|
Complementary
|
No
|
No
|
8
|
533
|
0.61
|
|
Pseudo-NMOS
|
Yes
|
Yes
|
5
|
288
|
1.49
|
|
CPL
|
No
|
No
|
14
|
800
|
0.75
|
|
Dynamic (np)
|
No
|
No
|
6
|
212
|
0.37
|
