ITRS (International Technology Roadmap for Semiconductors)

ITRS ( International Technology Roadmap for Semiconductors)

The unique factor that has made the semiconductor industry successful:

" Decreases in feature size have provided improved functionality at a reduced cost ".

Traditional scaling to Equivalent scaling :

Traditional scaling is starting to be effected by fundamental limits of the materials constituting the building blocks of the planar CMOS process.

Continuing the 2x/2years performance improvement will be achieved through the assimilation of new materials for next 5-10 years (called equivalent scaling).
New devices needed in 10-15 years (alternative to planar CMOS).

In addition to new materials, need innovations in circuit and system design to maintain rate which:
Integrate multiple silicon technologies on same chip.
Closely integrate package and silicon technology.

Emerging product catagory: Performance System-on-a-Chip ( P-SoC ).

ITRS

Feature scaling enables improvements to the following trends:

Trend	Example
Functionality	Nonvolatile memory
Integration Level	Components/chip (Moore's Law)
Compactness	Components/cm2
Speed	Microprocessor clock
Power	Laptop or cell phone battery life
Cost	Cost-per-function (decreases at >25%/year)

Most of these trends have been exponential.

DRAM 1/2 pitches (cell area) of six roadmap "technology nodes":

Year	1999	2002	2005	2008	2011	2014
Tech node	180	130	100	70	50	35

Each node is approximately 70% of the previous node.

System-on-a-Chip (SoC):

Popular in digital communications equipment.
Often mixed-technology designs incorporating:
Embedded DRAM
High-performance or low-power logic
Analog components
RF components
Plus possibly Micro-ElectroMechanical Systems ( MEMS ) and optical input/output.

For cost and time-to-market reasons, specific SoC architectures will be developed and customized for a specific product through programming.

Software, FPGAs, Flash, etc. will be used to configure these programmable platforms.

Hot research topics:

Design tools are needed to assemble, verify and program them.

Design and Test Complexity Issues

Design complexity is increasing super-exponentially because of:
Increased density.
Increased number of transistors.
Increased design heterogeneity (SoC).
Increasing number of factors that design tools and methods must consider with smaller feature sizes and higher levels of integration.

Design and test complexity issues:
Silicon complexity increased:

With larger number of interacting devices and interconnects.
With impact of new technologies.
With impact of new logic families to meet performance goals.
With effects of power and current requirements.

System complexity increased:

With increased system size.
Diversity of SoC design styles, integrated passive components and embedded software.

Design and Test Complexity Issues

Design and test complexity issues (cont.):
Design procedure complexity increased:

With growing interaction between design levels.
With difficulties of convergence and predictability of the design process.
With increases in size and dispersion of design teams.

Verification complexity increased:

With need to validate core-based and mixed-technology designs.
With the need to validate timing and function together.
With the need to validate behavior at the system level.

Test complexity increased:

With higher speeds.
With higher levels of integration.
With greater design heterogeneity.
With reduced external access ( test-through-pins less viable).

Test Issues

Basic requirements:
High test reliability

Lower yield loss and field failure rates (higher device quality).

Low test costs.

New test requirements needed now (for technology > 100nm):
The ability to test for new failure modes, such as cross-talk induced failures caused by high density interconnect.
Testing embedded mixed analog/digital circuits.
Use of Design-for-Test (DFT) for testing high-speed devices using both low-cost and low-speed testers.

BIST offers potential solution for the latter two problems.

For technology < 100nm:
Testing of SoC.

Need for higher-order DFT.

Built-In-Self-Repair will be explored as a means of salvaging chips.

Process Integration Issues:

Past trends in DRAM chip size: 1.4x every 4x in bit capacity.

Continuation would make chip sizes too large, leading to problems with the size of lithographic exposure areas and packaging.
New model is 1.2x, which requires development of new "smaller" cells.

Open-bit-line cell.
Cross-point-cell.

Further scaling of MOSFETs for higher performance and minimum variation in product specification may require:

For technologies > 100nm:

Halo doping (as a channel formation technology).
High-mobility silicon-germanium epitaxial layer .

For technologies < 50nm:

Novel switching devices such as quantum-dot or single-electron transistors.
New storage devices such as ferroelectric RAMs (FeRAMs) and MRAMs.

Process Integration Issues:

For analog and mixed-signal devices, noise problems must be addressed for V _DD s of 2.0-1.5V.

Other challenges include:
Building high capacitance structures

Solution: high k dielectric materials.

Minimizing parasitic capacitance:

Solutions:

Low k dielectric materials.
Copper interconnect.
SOI substrates.
3-dimensional structures.

For SoC:

Mixing embedded memory, logic and analog circuit creates noise problems that must be dealt with.
Processes that support the large number of steps for mixed technology.

Front End Process Issues:

Tech. breakthroughs in materials and processes needed for further scaling.

Issues:
The use of physically "thicker" (than silicon dioxide) gate materials to minimize tunnel current through gate while maintaining high-capacitance.
The use of metal gate electrodes to compensate for slower processing speeds caused by depletion in poly.
Methods for forming ultra-thin and low-sheet resistance pn junctions for higher performance transistors.

New materials for gates and dielectrics make gate etching process more difficult.

For technologies > 100nm (65 nm gate length), solutions include:
Silicon nitride, unary metal oxides and silicates, for thinox.
Raised source/drain, plasma doping and laser annealing methods for junctions.
Ru for electrodes.

Lithography Issues:

70% reduction has been achieved within 2-3 years through:
Shorting the wavelength of light sources.
Increasing numerical aperture for optical systems.
Using half-tone phase-shift masks and other resolution enhancing technologies.

Optical lithography may be extended through the use of:
The development of 157 nm technology (using F₂ laser light and alternating phase-shift masks and other high resolution techniques).

Problem: 157 nm is absorbed by oxygen and organic materials, so oxygen free exposure environment necessary.

Other solutions include:
Extreme Ultraviolet
Electron Projection Lithography
Electron-beam direct-write proximity X-ray lithography.
Plus others.

Lithography Issues:

Mask-making capability and cost escalation have become the major limiter to lithography progress.

The mask industry has fallen behind requirements of the chipmakers.

A challenge to all "tech" nodes:
Controlling critical dimensions.
Overlays.
Defect density.

For nodes < 100nm, difficulty is related to absolute sizes.

For example, processing dimensions are getting close to sizes of photoresist molecules and other physical distances.

Existing techniques for measuring sizes, positions and defects are becoming difficult to use.

Displacement of equipment's structural parts due to heat and vibration is no longer negligible.

Interconnect Issues:

Objective is to distribute clock and other signals to provide power/ground to various circuits on the chip.

As supply voltage is scaled or reduced, cross-talk has become an issue for all clock and signal wiring levels.

Near term solution adopted by industry is to make copper wires thinner to reduce line-to-line capacitance.

This must be combined with new insulator materials, for the short term.

For the long term, new design or technology solutions are needed to overcome the performance limitations of traditional interconnect:
Coplanar waveguides.
Free space RF.
Optical interconnect.

Defect Reduction:

Defect reduction is a continuing challenge common to all technology nodes, as a means of maintaining high product yield.

Approximately 80X increase in data processing required for correct trouble shooting from 180nm to 50nm node.

The requirements for defect detection and defect analysis (failure analysis) equipment is becoming more stringent:

UV defect inspection equipment for wafers is failing at the 130nm node.

Traditional failure analysis will be inadequate in several ways:
The classification speed of defects.
The number of defects that can be handled.
The speed of chemical element analysis.

New defect detection equipment must be developed to satisfy the requirements for lower defect rates.

Other Issues:

Factory Integration:

Focuses on:

Wafer processing aspect of fabrication (large diameter wafers).
The complexity introduced by the diversification of processes.
The increased reliance on factory automation.

Tech node (nm)	180	130	100	70	50	35
Non Hot Lot production period/mask layer (days)	1.8	1.6	1.4	1.3	1.2	1.1
Hot Lot production period/mask layer (days)	0.9	0.85	0.8	0.75	0.7	0.65

Assembly and Packaging:

Focuses on:

Reducing package size.

Area array used for logic chips with >800 pins.
Flip-chip connection in ball grid arrays (BGAs) for further reduction.

Reducing the effective dissipation of heat.

Other Issues:

Modeling and Simulation:

Cost reductions up to 35% can be achieved at the 130/100nm nodes through the use of modeling and simulation of processes, electrical characteristics, heat and reliability.

Metrology

Environment, Safety and Health