Scaling

• Current technology node is 0.18 m m and there is a move to 0.13mm underway.

• The size of the circuits also continues to increase.
• Besides increasing the number of devices, scaling has had a profound impact on both speed and power.

Scaling

• Full scaling ( Constant Electrical Field Scaling )
• In the ideal model, all the dimensions of the MOS devices, e.g., the voltage supply level and depletion widths are scaled by the same factor S .

 

• Keeping the electric field patterns constant avoids breakdown and other secondary effects.

 

• This leads to greater device density, higher speed and reduced power consumption.

 

• Performance is improved because of the reduced capacitance and reduced voltage swing .

 

• Circuit speed increases linearly while the power-delay product is reduced in a cubic fashion!
• Both clearly indicate the benefits of scaling.

Scaling

Parameter	Relation	Full Scaling	General Scaling	Fixed-V Scaling
W, L, tox		1/S	1/S	1/S
VDD, VT		1/S	1/U	1
NSUB	V/Wdepl2	S	S2/U	S2
Area/Device	WL	1/S2	1/S2	1/S2
Cox	1/tox	S	S	S
CL	CoxWL	1/S	1/S	1/S
kn, kp	CoxW/L	S	S	S
Iav	kn,pV2	1/S	S/U2	S
Jav	Iav/Area	S	S3/U2	S3
tp(intrinsic)	CLV/Iav	1/S	U/S2	1/S2
Pav	CLV2/tp	1/S2	S/U3	S
PDP	CLV2	1/S3	1/SU2	1/S

• See text for assumption used to derive this table.

 

• Dimensions are scaled by S while voltages are scaled by U .

Scaling

• Full scaling is not a feasible option.
• For example, to keep new chips compatible with existing chips, voltages cannot be scaled arbitrarily.

 

• Providing multiple voltage supplies is expensive.

 

• 5V was used up through the mid 90s.
• Recently we've seen voltages of 3.3, 3.0 and 1.5 used internally.

 

• Plus, some device voltages, e.g., silicon bandgap and built-in junction potential , are material parameters and cannot be scaled.

 

• Finally, V _T scaling is limited since making it too low makes it difficult to turn off the devices completely.
• This is aggravated by large process variations.

 

• A more general scaling model is needed, where dimensions and voltages are scaled independently.

Scaling

• General Scaling
• Device dimensions are scaled by a factor S while voltages are scaled by a factor U .

 

• Under constant voltage scaling, U = 1 as shown in the last column of the table.

 

• Under this model, currents are increased by a factor of S .

 

• This results in a rather impressive speed-up (1/ S ² ) at the expense of increased power consumption ( S ).

Scaling

• Note that this model ignores a number of second-order effects, e.g.,
• Mobility degreadation, velocity saturation, drain-induced barrier lowering and series resistances.

 

• The effects of velocity saturation can be significant.

Parameter	Relation	Full Scaling	General Scaling	Fixed-V Scaling
Iav	CoxWV	1/S	1/U	1
Jav	Iav/Area	S	S2/U	S2
tp(intrinsic)	CLV/Iav	1/S	1/S	1/S
Pav	CLV2/tp	1/S2	1/U2	1

• Reduces voltage dependency of I _av from quadratic to linear .

 

• The decrease in propagation delay with S is not as large as predicted by previous table.