-
In sequential logic, the outputs depend not only on the inputs, but also on the preceding input values... it has memory.
-
Memory can be implemented in 2 ways:
-
Positive feedback or
regeneration
(static):
-
One or more output signals are connected back to the inputs via storage elements.
-
These circuits are called
multivibrator
.
-
Bistable
elements such as flip-flops are most common but
monostable
and
astable
circuits are also used.
-
Charge storage (dynamic):
-
As we know, a periodic refresh is necessary here.
-
The
bistable
element can be either static or dynamic and is an essential library element called a register.
-
An
astable
multivibrator acts as an oscillator (clock generator) while a
monostable
multivibrator can be used as a pulse generator.
-
We've already discussed the regenerative property.
-
If the gain of the inverter in the transient region is
greater than 1
, there are only two stable operating points.
-
Storing a new value usually involves applying a
trigger pulse
for a duration equal to the propagation delay through the two inverters.
-
The trigger pulse takes either V
i1
or V
i2
temporarily out of the region where the gain,
G
, is
less than 1
to the unstable region where
G
> 1.
-
The ambiguity of having a
non-allowed mode
caused by trigger pulses going active simultaneously can be avoided by adding two feedback lines:
-
Note if both
J
and
K
are high, and clock pulses, the output is complemented.
-
However, doing so enables the other input and the FF
oscillates
.
-
This places some stringent constraints on the
clock pulse width
(e.g. < than the propagation delay through the FF).
-
Synchronous circuit:
-
Changes in the output logic states of all FFs are synchronized with the clock signal, f.
-
Note that:
-
T FF (
toggle FF
) is a special case of the JK with J and K tied together.
-
D FF (
delay FF
) is a special case with J and K connected with complementary values of the D input.
-
It generates a delayed version of the input synchronized with the clock.
-
These FFs are also called
latches
.
-
A FF is a latch if the gate is transparent while the clock is high (low).
-
Any changes in the input appear in the output after a nominal delay.
-
The transparent nature can cause
race
problems:
-
One way to avoid the race is to use the master-slave approach.
-
The master on the left is active (
J
and
K
are enabled) when
f
is high.
-
The slave on the right is in hold mode, preventing changes on
SI
and
RI
from propagating to the output,
Q
.
-
When
f
goes low, the state of the master is frozen and the NAND gates in the slave are enabled.
-
There is no constraint on the
maximum
width of
f
for proper operation.
-
Problem with master-slave approach:
-
The circuit is sensitive to changes in the input signals as long as
f
is high.
-
In the case of the JK FF, the inputs MUST stay constant with
f
high.
-
If FF is reset, it is sensitive to the level of
J
, e.g., 1 glitches.
-
The fix is to allow the state of the FF to change only at the rising (falling) edge of the clock.
-
The modification applied to the
JK
FF is shown below.
-
Note that the inputs must be stable for some time before the clock goes low.
-
This is also true for the master-slave D FF, but the constraints are different.
-
Let's first define some terms.
-
Timing diagram showing the terms defining the proper operation of a FF.
-
Tc: Clock Cycle Time.
-
T
s
: The amount of time
before
the clock edge that the D input has to be stable.
-
T
h
: Data has to be held for this period while clock travels to point of storage.
-
T
q
: Clock-to-Q delay: Delay from the positive clock input to new value of Q.
-
Depending on the design, one or both of T
s
and T
h
may have to be non-zero.
-
For example, the master-slave D FF is likely to require a longer setup time than the edge-triggered D FF.
-
Edge triggered FF prevents the "master" from following the
D
input so the FF's internal delay does not affect setup time.
-
Two possible strategies to implement clocked systems:
-
Latches are a more economical implementation strategy but are transparent on half of the clock cycle, and cannot be used in feedback systems.
-
Also, the following constraint must be met for latches:
-
T
d
< T
c
/2 - T
q
- T
s
-
where T
d
is the worst case propagation delay, T
c
is the clock cycle time, T
q
is the Clock-to-Q time of latch A and T
s
is the setup time for latch B.
-
For edge-triggered FFs, the following time constraint must be met:
-
Clock races caused by:
-
Delays in the clock line to Reg B.
-
New data stored instead of previous data:
-
Delays in the combinational logic that are larger than the clock cycle time.
-
Data arrives late at Reg B, old data retained instead of latching new data.
-
As you can see, designers have to walk a temporal 'tight-rope', e.g., they have to minimize clock skew while considering worst and best case delays through combinational logic.
-
Full complementary version of the master-slave FF requires 38 transistors!
