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Design description for an IC may be described in three domains:
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Behavioral
(sequential verses parallel algorithms)
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Structural
(logic family, clocking strategy and circuit style)
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Physical
(layout of chips and boards)
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Each of these domains may be hierarchically divided into levels of design abstraction.
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Architectural or functional level
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Register-transfer level (RTL)
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Logic level
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Circuit level
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Design is a continuous trade-off to achieve adequate results for the following design parameters:
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Performance (speed, power, function and flexibility.)
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Size of die.
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Time to design.
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Ease of test generation and testability.
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Classical techniques for reducing the complexity of IC design:
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Hierarchy
:
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Divide and conquer: Divide a module into submodules - repeat until complexity of submodule is comprehensible.
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Behavioral
: A subroutine that describes the behavior of an adder.
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Structural
: A schematic (transistor-level) diagram that shows the circuit structure.
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Physical
: Layout of the adder.
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Regularity
:
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Objective is to produce a set of similar building blocks as a design is hierarchically decomposed.
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Behavioral
: The reuse of an adder subroutine in different modules of a processor.
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Structural
: The reuse of the same implementation of a multiplexer in higher level system entities.
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Physical
: The use of uniformly sized transistors - don't optimize.
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Modularity
:
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The tenet of modularity adds to hierarchy and regularity the condition that submodules have well-defined functions and interfaces.
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Documentation of modules define the position, name, layer type, size and signal type of external interconnections, along with logic function and electrical characteristics.
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Especially useful for team designs.
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Bad use of modularity might involve the use of transmission gates at the inputs to a module. Buffering them with inverters improves the modularity.
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Locality
:
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Temporal and spacial locality can be applied to the organization of a set of modules that compose a design.
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Time locality
: Modules see a common clock - requires attention to clock generation and distribution strategy.
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Spacial locality
: Minimize global wiring by "wiring first, than placing the modules".
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Arranged in order of "increased design investment".
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Programmable Logic
:
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Chips with programmable logic structures.
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Chips with programmable interconnect.
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Chips with reprogrammable gate arrays.
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PAL
(Programmable Array Logic) or
PLD
(Programmable Logic Devices):
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Programming of PALs done by:
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Fusible links
:
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One-time programming.
-
Current used to blow links made of platinum silicide or titanium tungsten.
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UV-erasable EPROM
:
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Reprogrammable with UV light.
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High voltage (~14 volts) applied to a floating gate interposed between regular MOS transistor gate and channel.
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EEPROM
:
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ROM cells reprogrammable electrically.
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Two transistors used in a ROM cell, an access transistor to program and a programmed transistor.
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Floating gate structure used here as well.
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Programmable Interconnect
:
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Voltage used to stress dielectric to breakdown reducing resistance between two wires from 100 MOhms to 200-500 Ohms.
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Reprogrammable Gate Arrays
:
-
Two categories:
Structured
and
ad-hoc
array: XILINX uses ad-hoc.
-
Reprogrammable Gate Arrays
:
-
CLB configuration of the XC4000 FPGA.
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Other options already discussed:
-
Sea-of-Gates
and
Gate Array Design
:
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Master or base wafers processed up though transistor formation.
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Personalization is achieved by using design-specific metalization and contacts.
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Standard Cell
:
-
Provide a density advantage over Gate Arrays at the cost of increased prototype costs and design complexity.
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Library of SSI logic blocks typically come in a density-optimized version and a speed-optimized version.
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Full-custom Mask Design
:
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Rarely used today because of high labor content and low productivity.
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Exceptions include:
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The design of memory and commodity parts such as FPGAs.
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The design of large mega-cells such as RISC microprocessors.
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Typical design process from start to finish:
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Behavioral level
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RTL level
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Logic level
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Structural level
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Layout level
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Tools exist to synthesize a chip layout from any of these levels of specification.
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Behavior Synthesis
:
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Silicon compilers: Take design written in behavioral code to mask level.
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i.e.
-
a = a + b*c (multiply-accumulate operation)
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Could be implemented using a bit-serial multiplier or a fully parallel Booth-encoded Wallace tree multiplier.
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Technology independent but limited in capabilities - this is changing !
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RTL Synthesis
:
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Take an RTL description and convert it to a set of registers and combinational logic.
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Logic optimization is then used to improve the logic to meet timing and area constraints.
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RTL descriptions are captured using a
Hardware Description Language
(HDL).
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We've seen examples of this in VHDL where we used control flow (if-then-else/case) statements, hierarchy, word widths, bit vectors, arithmetic, logic and comparison operations.
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Logic Optimization
:
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These programs take logic descriptions produced by RTL synthesis, strip out the registers and optimize the network of gates (using a given logic library).
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Registers are then reunited with optimized logic and layout generated automatically.
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Objective: Manipulate logic to meet speed or area constraints or both.
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Tech independent phase (logic optimization) followed by tech-mapping phase to std cells, FPGA, etc.
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Logic Optimization
:
Technology-independent
phase.
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Network organization: Remove constant nodes and redundant inverters then convert to a two-level PLA sum-of-products.
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Two-level minimization (Espresso).
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Algebraic decomposition: Introduces new nodes into the network in a manner that minimizes the cost.
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Weak division
: Decomposes two-level into multiple-level logic expressions by dividing the expressions by subexpressions that appear more than once: i.e.,
-
Reducing the number of literals reduces area.
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Manipulating the number of logic levels improves speed.
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Iterative improvement: Algebraic techniques of extraction, factoring and substitution.
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Logic Optimization
:
Technology-dependent
phase.
-
Technology mapper is then used to optimize the gates for a particular technology.
-
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Two types of optimizers,
Rule based
and
Directed-Acyclic-Graph
(DAG) covering:
-
Rules may also bias gate selection toward faster gates, i.e. NAND gates.
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Logic Optimization
:
Technology-dependent phase.
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Structural-to-Layout Synthesis
:
-
Logic network and registers are automatically converted to layout.
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Placement
:
-
Task of placing modules adjacent to each other to minimize area or cycle time.
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Two main algorithms:
-
Min-cut algorithm
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Thermal annealing
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Routing
:
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Takes a module placement and a list of connections and connects the modules with wires.
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Three classes (in order of increasing capability):
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Channel routers
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Switchbox routers
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Maze routers.
