Verilog HDL

• A verilog model is a description of a design in Verilog HDL.
• Verilog supports
• Behavioral models : Describe the function.
• Structural models : Describe the components and connections of the components.

 

• Verilog supports several levels of abstraction:
• Algorithmic
• A model that implements a design algorithm in high-level language constructs.
• RTL
• A model that describes the flow of data between registers and how a design processes that data.
• Gate-level
• A model that describes the logic gates and the connections between logic gates in a design.
• Switch-level
• A model that describes the transistors and storage nodes in a device.

Verilog Gate-Level Example

• 2-Bit Adder

• 1) K&R C style of declaration to a module.
• 2) Instantiate the gate with delay (optional), instance name (optional), and I/O where the output is the leftmost operand.
• 3) Instantiate half_adder with module name, instance name and I/O. Connection between caller and callee are order based in this example.

Verilog Gate-Level Example

• 2-Bit Adder

• 4) Inputs a and b are both 2-bit vectors.
• 5) Specify the data types for a , b and sum , in this case they are wire .

 

• The module is the basic building block.
• A design can be hierarchically decomposed into a set of modules.

Verilog Capability Overview

• Behavioral constructs are used for algorithmic and RTL models.

 

• Capabilities include:
• Structured procedures for sequential or concurrent execution.
• Explicit control of the time of procedure activation specified by both:
• Delay expressions.
• Value changes called event expressions.
• Procedural constructs for conditional, if-else, case and looping operations.
• Procedures called tasks that can have parameters and non-zero time duration.
• Procedures called functions that allow the definition of new operators.
• Arithmetic, logical, bitwise and reduction operators for expressions.

Verilog HDL Capability Overview

• Structural constructs are used for gate-level and switch-level models.

 

• Capabilities include:
• A complete set of combinational primitives.
• Primitives for bidirectional pass and resistive devices.
• The ability to model dynamic MOS models with charge sharing and charge decay.

The Verilog-XL Logic Simulator

 

• Simulation allows you to perform several tasks BEFORE you build the prototype.
• Determine the feasibility of the new design.
• Try more than one approach to a design problem.
• Verify functionality.
• Identify design errors.

 

• Verilog-XL has the following capabilities:
• Set break points during simulation that stops the simulation and allows you to enter an interactive mode to examine and debug your design.
• Apply stimulus during simulation.
• Patch circuits during simulation.
• Traverse the model hierarchy to various regions of your design to examine the state of the simulation in that region.
• Single step through the statements of a design.
• Save the current state so that you can resume later.
• Use stochastic modeling techniques.

Verilog-XL

• Lexical Conventions:
• Numbers : < size >< base_format >< numbers >
• < size > (optional): Specify a constant in exact number of bits.
• < base_format > (optional): A letter specifying the number's base.
• Letters include `d , `h , `o or `b .
• < number >: The value of the constant:

 

• Numbers can also be high impedance using a z or ? character.

Ve rilog-XL

• Lexical Conventions:
• Strings :
• Strings are represented in the usual way as "I'm a string" except that there is no termination character.
• To declare storage for them, declare a register large enough to hold the constant.
• For example, to store "Hello World!" requires 12 8-bit ASCII characters:

• Output is:

Verilog-XL

• Lexical Conventions:
• Identifiers :
• They are case sensitive.
• They start with a letter or an underscore and can contain letters , underscores , dollar signs ( $ ) and digits .

 

• Macros :
• Defined similarly to C (of course).
• Begin with accent grave (`):

• Use as: