Verilog-XL

• Gate- and Switch-Level Modeling.
• A logic network can be modeled using:
• Continuous assignments.
• Switches and logic gates.

 

• Switches and Logic gate modeling advantages:
• Gates provide a much closer one-to-one mapping between the actual circuit and the network model.
• There is no continuous assignment equivalent to the bidirectional transfer gate (transmission gate).
• Gate require smaller amounts of memory to simulate.
• Simulation time is likely to be shorter as well with gates.

Verilog-XL

• Gate- and Switch-Level Modeling.
• Gate and Switch declaration components:
• A keyword that names the type of gate or switch primitive.
• The drive strength specification.
• The delay specification .
• The identifier that names each gate or switch instance .
• An optional range specification for an array of instances.
• The terminal connection list in primitive gate or switch instances.

 

• A gate declaration begins with the <GATETYPE> keyword.

Verilog-XL

• Gate- and Switch-Level Modeling.
• Drive Strength specifies the strengths of the values on the output terminals.
• Available for the following gate primitives:
• and, nand, or, nor, not, notif0, notif1
• xor, xnor
• buf, bufif0, bufif1
• pulldown, pullup

 

• The drive specification has two parts, which must both be present or none at all (except for pulldown and pullup).
• Strength values available:

• highzx values cause the gate to output a z.
• Default is strong1 and strong0 if not specified.

Verilog-XL

• Gate- and Switch-Level Modeling.
• Delay Specification specifies the propagation delay through the gates and switches in a declaration.
• A delay specification can contain up to three delay values.
• No delay specification results in a zero delay model.

 

• Primitive Instance Identifier is an optional name given to a gate or switch instance.
• Useful for debugging.
• An instance declared as an array must be named.

 

• Range Specification is used to specify an array of instances as [n:m]:

 

• Terminal Connection List describes how the gate or switch connects to the rest of the model.
• The output terminal is the leftmost terminal.

Verilog-XL

• Gate- and Switch-Level Modeling.
• Examples:

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