################################################
#                                              #
#  FirstEncounter Input configuration file     #
#                                              #
################################################

global rda_Input
set cwd /nfs/home/research/research/chip/ENCOUNTER/AES
set rda_Input(import_mode) {-treatUndefinedCellAsBbox 0 -keepEmptyModule 0 }
# This netlist is rebel incorporated and with puf instance, also removed stubs
set rda_Input(ui_netlist) "AES.v"
set rda_Input(ui_netlisttype) {Verilog}
set rda_Input(ui_ilmlist) {}
set rda_Input(ui_settop) {0}
set rda_Input(ui_topcell) {}
set rda_Input(ui_celllib) {}
set rda_Input(ui_iolib) {}
set rda_Input(ui_areaiolib) {}
set rda_Input(ui_blklib) {}
set rda_Input(ui_kboxlib) {}
set rda_Input(ui_gds_file) {}
#set rda_Input(ui_timelib,min) "../lib/*fast*.lib"
#set rda_Input(ui_timelib,max) "../lib/*slow*.lib"
set rda_Input(ui_timelib) "../../ELC/std_cells.lib"
set rda_Input(ui_smodDef) {}
set rda_Input(ui_smodData) {}
set rda_Input(ui_dpath) {}
set rda_Input(ui_tech_file) {}
#set rda_Input(ui_io_file) "dtmf.io"
set rda_Input(ui_io_file) {}
#set rda_Input(ui_timingcon_file) ""
set rda_Input(ui_timingcon_file) {AES.sdc}
set rda_Input(ui_latency_file) {}
set rda_Input(ui_scheduling_file) {}
#set rda_Input(ui_buf_footprint) {BUFX1}
set rda_Input(ui_buf_footprint) {}
#set rda_Input(ui_delay_footprint) {DLY1X1}
set rda_Input(ui_delay_footprint) {}
#set rda_Input(ui_inv_footprint) {INVX1}
set rda_Input(ui_leffile) "../../ABSTRACT/cms9flp.lef ../../ABSTRACT/std_cells.lef"
set rda_Input(ui_core_cntl) {aspect}
set rda_Input(ui_aspect_ratio) {1.0}
set rda_Input(ui_core_util) {0.7}
set rda_Input(ui_core_height) {}
set rda_Input(ui_core_width) {}
set rda_Input(ui_core_to_left) {}
set rda_Input(ui_core_to_right) {}
set rda_Input(ui_core_to_top) {}
set rda_Input(ui_core_to_bottom) {}
set rda_Input(ui_max_io_height) {0}
set rda_Input(ui_row_height) {}
set rda_Input(ui_isHorTrackHalfPitch) {0}
set rda_Input(ui_isVerTrackHalfPitch) {1}
set rda_Input(ui_ioOri) {R0}
set rda_Input(ui_isOrigCenter) {0}
set rda_Input(ui_exc_net) {}
set rda_Input(ui_delay_limit) {1000}
set rda_Input(ui_net_delay) {1000.0ps}
set rda_Input(ui_net_load) {0.5pf}
set rda_Input(ui_in_tran_delay) {0.0ps}
#set rda_Input(ui_captbl_file) "../captable/t018s6mlv.capTbl"
set rda_Input(ui_captbl_file) {}
#set rda_Input(ui_cap_scale) {1.0}
set rda_Input(ui_defcap_scale) {1.0}
set rda_Input(ui_detcap_scale) {1.0}
set rda_Input(ui_xcap_scale) {1.0}
#set rda_Input(ui_res_scale) {1.0}
set rda_Input(ui_preRoute_res) {1.0}
set rda_Input(ui_postRoute_res) {1.0}
set rda_Input(ui_shr_scale) {1.0}
set rda_Input(ui_time_unit) {none}
set rda_Input(ui_cap_unit) {}
set rda_Input(ui_oa_reflib) {}
set rda_Input(ui_oa_abstractname) {}
set rda_Input(ui_oa_layoutname) {}
set rda_Input(ui_sigstormlib) {}
#set rda_Input(ui_cdb_file) "../cdb/tsmc18.ss.cdB"
set rda_Input(ui_cdb_file) {}
#set rda_Input(ui_echo_file) "../cdb/macro.udn"
set rda_Input(ui_echo_file) {}
set rda_Input(ui_xilm_file) {}
set rda_Input(ui_qxtech_file) {}
set rda_Input(ui_qxlib_file) {}
set rda_Input(ui_qxconf_file) {}
set rda_Input(ui_pwrnet) {VDD!}
set rda_Input(ui_gndnet) {GND!}
set rda_Input(flip_first) {1}
set rda_Input(double_back) {1}
set rda_Input(assign_buffer) {0}
set rda_Input(ui_pg_connections) ""
set rda_Input(ui_gen_footprint) {1}