###############################################################
#  Generated by:      Cadence Encounter 09.11-s082_1
#  OS:                Linux x86_64(Host ID ece137a-2189.ece.unm.edu)
#  Generated on:      Tue Oct 26 10:49:38 2010
#  Command:           clockDesign -genSpecOnly Clock.ctstch
###############################################################
#
# Encounter(R) Clock Synthesis Technology File Format
#

#-- MacroModel --
#MacroModel pin <pin> <maxRiseDelay> <minRiseDelay> <maxFallDelay> <minFallDelay> <inputCap>

#-- Special Route Type --
#RouteTypeName specialRoute
#TopPreferredLayer 4
#BottomPreferredLayer 3
#PreferredExtraSpace 1
#End

#-- Regular Route Type --
#RouteTypeName regularRoute
#TopPreferredLayer 4
#BottomPreferredLayer 3
#PreferredExtraSpace 1
#End

#-- Clock Group --
ClkGroup
+ clk

RouteTypeName CLK_ROUTE
TopPreferredLayer 8
BottomPreferredLayer 1
#NonDefaultRule WideWire
PreferredExtraSpace 1
End

#------------------------------------------------------------
# Clock Root   : clk
# Clock Name   : clk
# Clock Period : 10ns
#------------------------------------------------------------
AutoCTSRootPin clk
Period         4ns
MaxDelay       0.5ns
MinDelay       0ns
MaxSkew        150ps
SinkMaxTran    200ps
BufMaxTran     200ps
AddDriverCell  INVX1 INVX2 INVX4 INVX8 INVX16 INVX24 INVX32
Buffer         BUFX4 BUFX8 BUFX16 BUFX32
NoGating       NO
DetailReport   YES
SetDPinAsSync  YES
SetIoPinAsSync YES
RouteClkNet    YES
RouteType      CLK_ROUTE
END

#------------------------------------------------------------
# Clock Root   : clk2
# Clock Name   : clk2
# Clock Period : 2ns
#------------------------------------------------------------
#AutoCTSRootPin clk2
#Period         2ns
#MaxDelay       2ns
#MinDelay       0ns
#MaxSkew        150ps
#SinkMaxTran    200ps
#BufMaxTran     200ps
#AddDriverCell  CLKBUFX16
#Buffer         CLKINVX8 CLKINVX12 CLKINVX16
#NoGating       NO
#DetailReport   YES
#SetDPinAsSync  YES
#SetIoPinAsSync YES
#RouteClkNet    YES
#RouteType      CLK_ROUTE
#END