-- -- $Author: tjkwon $ -- ========================================================================== -- RCS Path and File Name: $Source: /nfs/cadtools/tecvs/cvsroot/tecvs/ta0/design/rtl/fpu.vhd,v $ -- File Name: $RCSfile: fpu.vhd,v $ -- RCS File Release: $Revision: 1.2 $ -- Last Modified: $Date: 2007/10/09 02:59:12 $ -- Locked by: $Locker: $ -- -- Author : USC-ISI -- -- ========================================================================== -- $Log: fpu.vhd,v $ -- Revision 1.2 2007/10/09 02:59:12 tjkwon -- *** empty log message *** -- -- Revision 1.1 2007/10/09 02:57:53 tjkwon -- *** empty log message *** -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_misc.all; ENTITY fpu IS PORT( D0_flag : OUT std_logic; IV_flag : OUT std_logic; IX_flag : OUT std_logic; OV_flag : OUT std_logic; Result : OUT std_logic_vector(31 DOWNTO 0); UD_flag : OUT std_logic; OPCODE : IN std_logic_vector(2 DOWNTO 0); clk : IN std_logic; en : IN std_logic; en_Input : IN std_logic; oprA : IN std_logic_vector(31 DOWNTO 0); oprB : IN std_logic_vector(31 DOWNTO 0); start_Div : IN std_logic; reset : IN std_logic ); END fpu; ARCHITECTURE rtl OF fpu IS component DW_mult_pipe generic ( a_width : POSITIVE; b_width : POSITIVE; num_stages : POSITIVE; stall_mode : NATURAL; rst_mode : NATURAL); port ( clk : in std_logic; rst_n : in std_logic; en : in std_logic; tc : in std_logic; a : in std_logic_vector(32 downto 0); b : in std_logic_vector(25 downto 0); product : out std_logic_vector(58 downto 0) ); end component; component oprfmta port ( OPCODE_s1 : in std_logic_vector(2 downto 0); oprA_s1 : in std_logic_vector(31 downto 0); oprA_stat_s1 : in std_logic_vector(3 downto 0); signA_s1 : out std_logic; expA_s1 : out std_logic_vector(7 downto 0); fracA_s1 : out std_logic_vector(31 downto 0) ); end component; component oprfmtb port ( OPCODE_s1 : in std_logic_vector(2 downto 0); oprB_s1 : in std_logic_vector(31 downto 0); oprB_stat_s1 : in std_logic_vector(3 downto 0); signB_s1 : out std_logic; expB_s1 : out std_logic_vector(7 downto 0); fracB_s1 : out std_logic_vector(31 downto 0) ); end component; component count5 port( clk : in std_logic; en : in std_logic; en_Input : in std_logic; start_Div : in std_logic; OPCODE : in std_logic_vector(2 downto 0); OPCODE_s1 : in std_logic_vector(2 downto 0); cnt_s1 : out std_logic_vector(2 downto 0) ); end component; component comp_31b port( oprA_s1 : in std_logic_vector(31 downto 0); oprB_s1 : in std_logic_vector(31 downto 0); AeqB : out std_logic; AgrB : out std_logic; fracBgteA : out std_logic ); end component; component stage1_ctrl port( en : in std_logic; OPCODE_s1 : in std_logic_vector(2 downto 0); signA_s1 : in std_logic; signB_s1 : in std_logic; AeqB : in std_logic; AgrB : in std_logic; fracBgteA : in std_logic; cnt_s1 : in std_logic_vector(2 downto 0); Swap : out std_logic; sign_s1 : out std_logic; fracLsft : out std_logic; sel1_MD_s1 : out std_logic_vector(1 downto 0); sel2_MD_s1 : out std_logic_vector(1 downto 0); en_ALU1 : out std_logic; en_MD1 : out std_logic; enB : out std_logic ); end component; component expAddSub_9b_1 port( expG_s2 : in std_logic_vector(7 downto 0); expL_s2 : in std_logic_vector(7 downto 0); expCtrl_s2 : in std_logic_vector(1 downto 0); expAB_s2 : out std_logic_vector(8 downto 0); Cout_AB_s2 : out std_logic ); end component; component RSAgen port( expAB_s2 : in std_logic_vector(8 downto 0); OPCODE_s2 : in std_logic_vector(2 downto 0); rsa : out std_logic_vector(4 downto 0) ); end component; component ROM port( addr : in std_logic_vector(6 downto 0); x_s1 : out std_logic_vector(6 downto 0) ); end component; component stage2_ctrl port( en : in std_logic; OPCODE_s2 : in std_logic_vector(2 downto 0); AgrB_s2 : in std_logic; fracBgteA_s2 : in std_logic; oprA_stat_s2 : in std_logic_vector(3 downto 0); oprB_stat_s2 : in std_logic_vector(3 downto 0); cnt_s2 : in std_logic_vector(2 downto 0); oprG_stat_s2 : out std_logic_vector(3 downto 0); oprL_stat_s2 : out std_logic_vector(3 downto 0); fracOPsel : out std_logic; expCtrl_s2 : out std_logic_vector(1 downto 0); en_ALU2 : out std_logic; en_MD2 : out std_logic; en2_MD : out std_logic ); end component; component rshift_32b port( fracL_s2 : in std_logic_vector(31 downto 0); rsa : in std_logic_vector(4 downto 0); fracLrsh : out std_logic_vector(31 downto 0) ); end component; component sticky_1 port( fracL_s2 : in std_logic_vector(31 downto 0); OPCODE_s2 : in std_logic_vector(2 downto 0); rsa : in std_logic_vector(4 downto 0); Sticky1 : out std_logic_vector(4 downto 0); F2I_IX_s2 : out std_logic ); end component; component mux3_33b port( mux3_in : in std_logic_vector(32 downto 0); fracA_s2 : in std_logic_vector(24 downto 0); x_s2 : in std_logic_vector(6 downto 0); sel1_MD_s2 : in std_logic_vector(1 downto 0); MultIn0 : out std_logic_vector(32 downto 0) ); end component; component mux4_26b port( S_fwd : in std_logic_vector(25 downto 0); fracL_s2 : in std_logic_vector(31 downto 0); x_s2 : in std_logic_vector(6 downto 0); fracB_s2 : in std_logic_vector(30 downto 7); sel2_MD_s2 : in std_logic_vector(1 downto 0); MultIn1 : out std_logic_vector(25 downto 0) ); end component; component stage3_ctrl port( en : in std_logic; OPCODE_s3 : in std_logic_vector(2 downto 0); signA_s3 : in std_logic; signB_s3 : in std_logic; cnt_s3 : in std_logic_vector(2 downto 0); add_ctrl_ALU : out std_logic_vector(1 downto 0); en_ALU3 : out std_logic; en_MD3 : out std_logic; en3_MD : out std_logic; enALSB : out std_logic ); end component; component LZ_detect port( fracAddOut_s3 : in std_logic_vector(31 downto 0); OPCODE_s3 : in std_logic_vector(2 downto 0); oprG_stat_s3 : in std_logic_vector(3 downto 0); oprL_stat_s3 : in std_logic_vector(3 downto 0); fracZero_s3 : out std_logic; lz_s3 : out std_logic_vector(4 downto 0) ); end component; component fracAddSub_32b port( fracAddIn0_s3 : in std_logic_vector(31 downto 0); fracAddIn1_s3 : in std_logic_vector(31 downto 0); add_ctrl_ALU : in std_logic_vector(1 downto 0); fracAddOut_s3 : out std_logic_vector(31 downto 0) ); end component; component stage4_ctrl port( en : in std_logic; OPCODE_s4 : in std_logic_vector(2 downto 0); AddSub2Out : in std_logic_vector(33 downto 0); lz_s4 : in std_logic_vector(4 downto 0); cnt_s4 : in std_logic_vector(2 downto 0); lzOUT : out std_logic; fracRinSEL : out std_logic; expCtrl_s4 : out std_logic; sel3_MD : out std_logic; sel4_MD : out std_logic; selRin : out std_logic; add_ctrl_MD : out std_logic_vector(1 downto 0); en_ALU4 : out std_logic; en_MD4 : out std_logic; en4_MD : out std_logic; enAX : out std_logic; enQt : out std_logic; enDiv : out std_logic ); end component; component expBias_9b port( expAB_s4 : in std_logic_vector(8 downto 0); expCtrl_s4 : in std_logic; Cout_Bias_s4 : out std_logic; expBias_s4 : out std_logic_vector(8 downto 0) ); end component; component lshift_32b port( fracAddOut_s4 : in std_logic_vector(31 downto 0); lz_s4 : in std_logic_vector(4 downto 0); fraclsh : out std_logic_vector(31 downto 0) ); end component; component sticky_2 port( fracAddOut_s4 : in std_logic_vector(31 downto 0); lz_s4 : in std_logic_vector(4 downto 0); Sticky2 : out std_logic_vector(4 downto 0) ); end component; component tmpIX port( fracRin : in std_logic_vector(31 downto 0); tmpIX_s4 : out std_logic ); end component; component AddSub_1 port( AX : in std_logic_vector(33 downto 0); AddSub1In : in std_logic_vector(33 downto 0); add_ctrl_MD : in std_logic_vector(1 downto 0); AddSub1Out : out std_logic_vector(33 downto 0) ); end component; component AddSub_2 port( AddSub2In : in std_logic_vector(33 downto 0); add_ctrl_MD : in std_logic_vector(1 downto 0); roundup : in std_logic; AddSub2Out : out std_logic_vector(33 downto 0) ); end component; component Round1 port( OPCODE_s4 : in std_logic_vector(2 downto 0); fracRin : in std_logic_vector(31 DOWNTO 0); ALSB_s4 : in std_logic; MultOut_s4 : in std_logic_vector(58 DOWNTO 0); AddSub1OutMux1 : in std_logic_vector(33 DOWNTO 0); AddSub1OutMux2 : in std_logic_vector(33 DOWNTO 0); ROUND : out std_logic_vector(3 downto 0); tmpIX_MD_s4 : out std_logic ); end component; component Round2 port ( roundup : out std_logic; OPCODE_s4 : in std_logic_vector(2 DOWNTO 0); ROUND : in std_logic_vector(3 DOWNTO 0) ); end component; component stage5_ctrl port( en : in std_logic; OPCODE_s5 : in std_logic_vector(2 downto 0); AddSub2Out : in std_logic_vector(33 downto 0); lzLSB_s5 : in std_logic; FracMSB : in std_logic; MultOutMSB_s5 : in std_logic; cnt_s5 : in std_logic_vector(2 downto 0); expCtrl_s5 : out std_logic_vector(1 downto 0); expIn1sel : out std_logic; en5_MD : out std_logic ); end component; component expAddSub_9b_2 port( expIN1_s5 : in std_logic_vector(8 downto 0); lz_s5 : in std_logic_vector(4 downto 0); expCtrl_s5 : in std_logic_vector(1 downto 0); exp_s5 : out std_logic_vector(8 downto 0) ); end component; component EXCEPTION port( OPCODE_s5 : in std_logic_vector(2 downto 0); oprG_stat_s5 : in std_logic_vector(3 downto 0); oprL_stat_s5 : in std_logic_vector(3 downto 0); exp_s5 : in std_logic_vector(8 downto 0); lzLSB_s5 : in std_logic; F2I_IX_s5 : in std_logic; Cout_AB_s5 : in std_logic; Cout_Bias_s5 : in std_logic; F2I_IV_s5 : in std_logic; signA_s5 : in std_logic; signB_s5 : in std_logic; fracG_MSB_s5 : in std_logic; fracL_MSB_s5 : in std_logic; fracZero_s5 : in std_logic; tmpIX_s5 : in std_logic; tmpIX_MD_s5 : in std_logic; tmpUD_s5 : in std_logic; forceInf_I : out std_logic; D0_flag : out std_logic; IX_flag : out std_logic; IV_flag : out std_logic; OV_flag : out std_logic; UD_flag : out std_logic; forceInf : out std_logic; forceNaN : out std_logic; forceUD : out std_logic; forceZero : out std_logic ); end component; component ResFormat port( OPCODE_s5 : in std_logic_vector(2 downto 0); sign_s5 : in std_logic; exp_s5 : in std_logic_vector(8 downto 0); FRAC : in std_logic_vector(31 downto 0); forceNaN : in std_logic; forceInf : in std_logic; forceUD : in std_logic; forceZero : in std_logic; forceInf_I : in std_logic; Result : out std_logic_vector(31 downto 0) ); end component; component Squre port( Sq_in : in std_logic_vector(24 downto 6); r : out std_logic_vector(19 downto 1) ); end component; component Cube port( Cu_in : in std_logic_vector(24 downto 13); t : out std_logic_vector(12 downto 0) ); end component; component Accumul port( AddSub2Out_s5 : in std_logic_vector(33 downto 0); r : in std_logic_vector(19 DOWNTO 1); t : in std_logic_vector(12 DOWNTO 0); S : out std_logic_vector(25 downto 0) ); end component; SIGNAL OPCODE_s1 : std_logic_vector(2 DOWNTO 0); SIGNAL oprA_s1 : std_logic_vector(31 DOWNTO 0); SIGNAL oprB_s1 : std_logic_vector(31 DOWNTO 0); SIGNAL MultIn0 : std_logic_vector(32 DOWNTO 0); SIGNAL MultIn1 : std_logic_vector(25 DOWNTO 0); SIGNAL MultOut_s3 : std_logic_vector(58 DOWNTO 0); SIGNAL signA_s1 : std_logic; SIGNAL expA_s1 : std_logic_vector(7 DOWNTO 0); SIGNAL fracA_s1 : std_logic_vector(31 DOWNTO 0); SIGNAL signB_s1 : std_logic; SIGNAL expB_s1 : std_logic_vector(7 DOWNTO 0); SIGNAL fracB_s1 : std_logic_vector(31 DOWNTO 0); SIGNAL oprA_stat_s1 : std_logic_vector(3 DOWNTO 0); SIGNAL oprB_stat_s1 : std_logic_vector(3 DOWNTO 0); SIGNAL cnt_s1 : std_logic_vector(2 DOWNTO 0); SIGNAL tmp_cnt : std_logic_vector(2 DOWNTO 0); SIGNAL addr : std_logic_vector(6 DOWNTO 0); SIGNAL x_s1 : std_logic_vector(6 DOWNTO 0); SIGNAL fracBgteA : std_logic; SIGNAL AeqB : std_logic; SIGNAL AgrB : std_logic; SIGNAL Swap : std_logic; SIGNAL sign_s1 : std_logic; SIGNAL fracLsft : std_logic; SIGNAL en_ALU1 : std_logic; SIGNAL en_MD1 : std_logic; SIGNAL enB : std_logic; SIGNAL sel1_MD_s1 : std_logic_vector(1 DOWNTO 0); SIGNAL sel2_MD_s1 : std_logic_vector(1 DOWNTO 0); SIGNAL expG_s1 : std_logic_vector(7 DOWNTO 0); SIGNAL expL_s1 : std_logic_vector(7 DOWNTO 0); SIGNAL fracG_s1 : std_logic_vector(31 DOWNTO 0); SIGNAL fracL_s1 : std_logic_vector(31 DOWNTO 0); SIGNAL fracAlsft : std_logic_vector(24 DOWNTO 0); SIGNAL sign_s2 : std_logic; SIGNAL signA_s2 : std_logic; SIGNAL signB_s2 : std_logic; SIGNAL cnt_s2 : std_logic_vector(2 DOWNTO 0); SIGNAL oprA_stat_s2 : std_logic_vector(3 DOWNTO 0); SIGNAL oprB_stat_s2 : std_logic_vector(3 DOWNTO 0); SIGNAL OPCODE_s2 : std_logic_vector(2 DOWNTO 0); SIGNAL AgrB_s2 : std_logic; SIGNAL fracBgteA_s2 : std_logic; SIGNAL expG_s2 : std_logic_vector(7 DOWNTO 0); SIGNAL expL_s2 : std_logic_vector(7 DOWNTO 0); SIGNAL fracG_s2 : std_logic_vector(30 DOWNTO 7); SIGNAL fracL_s2 : std_logic_vector(31 DOWNTO 0); SIGNAL x_s2 : std_logic_vector(6 DOWNTO 0); SIGNAL sel1_MD_s2 : std_logic_vector(1 DOWNTO 0); SIGNAL sel2_MD_s2 : std_logic_vector(1 DOWNTO 0); SIGNAL fracA_s2 : std_logic_vector(24 DOWNTO 0); SIGNAL fracB_s2 : std_logic_vector(30 DOWNTO 7); SIGNAL ALSB_s2 : std_logic; SIGNAL expCtrl_s2 : std_logic_vector(1 DOWNTO 0); SIGNAL oprG_stat_s2 : std_logic_vector(3 DOWNTO 0); SIGNAL oprL_stat_s2 : std_logic_vector(3 DOWNTO 0); SIGNAL fracOPsel : std_logic; SIGNAL en_ALU2 : std_logic; SIGNAL en_MD2 : std_logic; SIGNAL en2_MD : std_logic; SIGNAL expAB_s2 : std_logic_vector(8 DOWNTO 0); SIGNAL Cout_AB_s2 : std_logic; SIGNAL rsa : std_logic_vector(4 DOWNTO 0); SIGNAL fracLrsh : std_logic_vector(31 DOWNTO 0); SIGNAL Sticky1 : std_logic_vector(4 DOWNTO 0); SIGNAL F2I_IX_s2 : std_logic; SIGNAL fracLmux : std_logic_vector(31 DOWNTO 0); SIGNAL F2I_IV_s3 : std_logic; SIGNAL Cout_AB_s3 : std_logic; SIGNAL fracL_MSB_s3 : std_logic; SIGNAL fracG_MSB_s3 : std_logic; SIGNAL signA_s3 : std_logic; SIGNAL signB_s3 : std_logic; SIGNAL sign_s3 : std_logic; SIGNAL cnt_s3 : std_logic_vector(2 DOWNTO 0); SIGNAL oprG_stat_s3 : std_logic_vector(3 DOWNTO 0); SIGNAL oprL_stat_s3 : std_logic_vector(3 DOWNTO 0); SIGNAL OPCODE_s3 : std_logic_vector(2 DOWNTO 0); SIGNAL expG_s3 : std_logic_vector(7 DOWNTO 0); SIGNAL expAB_s3 : std_logic_vector(8 DOWNTO 0); SIGNAL fracG_s3 : std_logic_vector(30 DOWNTO 7); SIGNAL fracAddIn1_s3 : std_logic_vector(31 DOWNTO 0); SIGNAL fracAddIn0_s3 : std_logic_vector(31 DOWNTO 0); SIGNAL F2I_IX_s3 : std_logic; SIGNAL ALSB_s3 : std_logic; SIGNAL add_ctrl_ALU : std_logic_vector(1 DOWNTO 0); SIGNAL lz_EXCEP : std_logic; SIGNAL en_ALU3 : std_logic; SIGNAL en_MD3 : std_logic; SIGNAL en3_MD : std_logic; SIGNAL enALSB : std_logic; SIGNAL fracZero_s3 : std_logic; SIGNAL lz_s3 : std_logic_vector(4 DOWNTO 0); SIGNAL fracAddOut_s3 : std_logic_vector(31 DOWNTO 0); SIGNAL fracZero_s4 : std_logic; SIGNAL F2I_IV_s4 : std_logic; SIGNAL Cout_AB_s4 : std_logic; SIGNAL fracL_MSB_s4 : std_logic; SIGNAL fracG_MSB_s4 : std_logic; SIGNAL signA_s4 : std_logic; SIGNAL signB_s4 : std_logic; SIGNAL sign_s4 : std_logic; SIGNAL cnt_s4 : std_logic_vector(2 DOWNTO 0); SIGNAL oprG_stat_s4 : std_logic_vector(3 DOWNTO 0); SIGNAL oprL_stat_s4 : std_logic_vector(3 DOWNTO 0); SIGNAL OPCODE_s4 : std_logic_vector(2 DOWNTO 0); SIGNAL expG_s4 : std_logic_vector(7 DOWNTO 0); SIGNAL expAB_s4 : std_logic_vector(8 DOWNTO 0); SIGNAL lz_s4 : std_logic_vector(4 DOWNTO 0); SIGNAL fracAddOut_s4 : std_logic_vector(31 DOWNTO 0); SIGNAL F2I_IX_s4 : std_logic; SIGNAL MultOut_s4 : std_logic_vector(58 DOWNTO 0); SIGNAL ALSB_s4 : std_logic; SIGNAL expCtrl_s4 : std_logic; SIGNAL fracRinSEL : std_logic; SIGNAL lzOUT : std_logic; SIGNAL add_ctrl_MD : std_logic_vector(1 DOWNTO 0); SIGNAL sel3_MD : std_logic; SIGNAL sel4_MD : std_logic; SIGNAL selRin : std_logic; SIGNAL en_ALU4 : std_logic; SIGNAL en_MD4 : std_logic; SIGNAL en4_MD : std_logic; SIGNAL enAX : std_logic; SIGNAL enDiv : std_logic; SIGNAL enQt : std_logic; SIGNAL Cout_Bias_s4 : std_logic; SIGNAL expBias_s4 : std_logic_vector(8 DOWNTO 0); SIGNAL tmpUD_s4 : std_logic; SIGNAL fraclsh : std_logic_vector(31 DOWNTO 0); SIGNAL Sticky2 : std_logic_vector(4 DOWNTO 0); SIGNAL fracRin : std_logic_vector(31 DOWNTO 0); SIGNAL tmpIX_s4 : std_logic; SIGNAL AddSub1In : std_logic_vector(33 DOWNTO 0); SIGNAL AX : std_logic_vector(33 DOWNTO 0); SIGNAL AddSub1Out : std_logic_vector(33 DOWNTO 0); SIGNAL AddSub1OutMux1 : std_logic_vector(33 DOWNTO 0); SIGNAL AddSub1OutMux2 : std_logic_vector(33 DOWNTO 0); SIGNAL AddSub2In : std_logic_vector(33 DOWNTO 0); SIGNAL AddSub2Out : std_logic_vector(33 DOWNTO 0); SIGNAL ROUND : std_logic_vector(3 DOWNTO 0); SIGNAL roundup : std_logic; SIGNAL tmpIX_MD_s4 : std_logic; SIGNAL Cout_Bias_s5 : std_logic; SIGNAL fracZero_s5 : std_logic; SIGNAL F2I_IV_s5 : std_logic; SIGNAL Cout_AB_s5 : std_logic; SIGNAL fracL_MSB_s5 : std_logic; SIGNAL fracG_MSB_s5 : std_logic; SIGNAL signA_s5 : std_logic; SIGNAL signB_s5 : std_logic; SIGNAL sign_s5 : std_logic; SIGNAL cnt_s5 : std_logic_vector(2 DOWNTO 0); SIGNAL oprG_stat_s5 : std_logic_vector(3 DOWNTO 0); SIGNAL oprL_stat_s5 : std_logic_vector(3 DOWNTO 0); SIGNAL OPCODE_s5 : std_logic_vector(2 DOWNTO 0); SIGNAL expG_s5 : std_logic_vector(7 DOWNTO 0); SIGNAL expBias_s5 : std_logic_vector(8 DOWNTO 0); SIGNAL lz_s5 : std_logic_vector(4 DOWNTO 0); SIGNAL tmpUD_s5 : std_logic; SIGNAL lzLSB_s5 : std_logic; SIGNAL tmpIX_s5 : std_logic; SIGNAL Qt : std_logic_vector(33 DOWNTO 8); SIGNAL F2I_IX_s5 : std_logic; SIGNAL MultOutMSB_s5 : std_logic; SIGNAL AddSub2Out_s5 : std_logic_vector(33 DOWNTO 0); SIGNAL tmpIX_MD_s5 : std_logic; SIGNAL expIN1sel : std_logic; SIGNAL expCtrl_s5 : std_logic_vector(1 DOWNTO 0); SIGNAL en5_MD : std_logic; SIGNAL expIn1_s5 : std_logic_vector(8 DOWNTO 0); SIGNAL exp_s5 : std_logic_vector(8 DOWNTO 0); SIGNAL forceInf : std_logic; SIGNAL forceNaN : std_logic; SIGNAL forceUD : std_logic; SIGNAL forceZero : std_logic; SIGNAL forceInf_I : std_logic; SIGNAL S : std_logic_vector(25 DOWNTO 0); SIGNAL S_fwd : std_logic_vector(25 DOWNTO 0); SIGNAL r : std_logic_vector(19 DOWNTO 1); SIGNAL t : std_logic_vector(12 DOWNTO 0); SIGNAL Sq_in : std_logic_vector(24 DOWNTO 6); SIGNAL Cu_in : std_logic_vector(24 DOWNTO 13); SIGNAL mux3_in : std_logic_vector(32 DOWNTO 0); SIGNAL FracMSB : std_logic; SIGNAL FRAC : std_logic_vector(31 DOWNTO 0); SIGNAL expa_az, expb_az, fraca_az, fracb_az : std_logic; SIGNAL expa_ao, expb_ao, fraca_nan, fracb_nan : std_logic; constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; BEGIN in_pipereg : process begin wait until clk = '1'; if reset = '0' then OPCODE_s1 <= "000"; oprA_s1 <= (others => '0'); oprB_s1 <= (others => '0'); else if en_Input = '1' then OPCODE_s1 <= OPCODE; oprA_s1 <= oprA; oprB_s1 <= oprB; end if; end if; end process in_pipereg; rom_in_reg : process begin wait until clk = '1'; if reset = '0' then addr <= (others => '0'); else if (start_Div = '1') then addr <= oprB(22 downto 16); end if; end if; end process rom_in_reg; expa_az <= not(or_reduce(oprA_s1(30 downto 23))); expb_az <= not(or_reduce(oprB_s1(30 downto 23))); fraca_az <= not(or_reduce(oprA_s1(22 downto 0))); fracb_az <= not(or_reduce(oprB_s1(22 downto 0))); expa_ao <= and_reduce(oprA_s1(30 downto 23)); expb_ao <= and_reduce(oprB_s1(30 downto 23)); fraca_nan <= or_reduce(oprA_s1(21 downto 0)); fracb_nan <= or_reduce(oprB_s1(21 downto 0)); oprA_stat_s1(0) <= expa_az and fraca_az ; -- zero? oprB_stat_s1(0) <= expb_az and fracb_az ; -- zero? oprA_stat_s1(1) <= expa_ao and fraca_az ; -- inf? oprB_stat_s1(1) <= expb_ao and fracb_az ; -- inf? oprA_stat_s1(2) <= expa_ao and fraca_nan ; -- NaN? oprB_stat_s1(2) <= expb_ao and fracb_nan ; -- NaN? oprA_stat_s1(3) <= expa_az and not fraca_az ; -- deNorm? oprB_stat_s1(3) <= expb_az and not fracb_az ; -- deNorm? I_oprfmta : oprfmta port map ( OPCODE_s1 => OPCODE_s1, oprA_s1 => oprA_s1, oprA_stat_s1 => oprA_stat_s1, signA_s1 => signA_s1, expA_s1 => expA_s1, fracA_s1 => fracA_s1 ); I_oprfmtb : oprfmtb port map ( OPCODE_s1 => OPCODE_s1, oprB_s1 => oprB_s1, oprB_stat_s1 => oprB_stat_s1, signB_s1 => signB_s1, expB_s1 => expB_s1, fracB_s1 => fracB_s1 ); I_count5 : count5 port map ( clk => clk, en => en, en_Input => en_Input, start_Div => start_Div, OPCODE => OPCODE, OPCODE_s1 => OPCODE_s1, cnt_s1 => cnt_s1 ); I_comp_31b : comp_31b port map( oprA_s1 => oprA_s1, oprB_s1 => oprB_s1, AeqB => AeqB, AgrB => AgrB, fracBgteA => fracBgteA ); I_stage1_ctrl : stage1_ctrl port map( en => en, OPCODE_s1 => OPCODE_s1, signA_s1 => signA_s1, signB_s1 => signB_s1, AeqB => AeqB, AgrB => AgrB, fracBgteA => fracBgteA, cnt_s1 => cnt_s1, Swap => Swap, sign_s1 => sign_s1, fracLsft => fracLsft, sel1_MD_s1 => sel1_MD_s1, sel2_MD_s1 => sel2_Md_s1, en_ALU1 => en_ALU1, en_MD1 => en_MD1, enB => enB ); expG_s1 <= expB_s1 when Swap = '1' else expA_s1; expL_s1 <= expA_s1 when Swap = '1' else expB_s1; fracG_s1 <= fracB_s1 when Swap = '1' else fracA_s1; fracL_s1 <= fracA_s1 when Swap = '1' else fracB_s1; fracAlsft <= fracG_s1(30 downto 7) & '0' when fracLsft = '1' else '0' & fracG_s1(30 downto 7); I_expAddSub_9b_1 : expAddSub_9b_1 port map( expG_s2 => expG_s2, expL_s2 => expL_s2, expCtrl_s2 => expCtrl_s2, expAB_s2 => expAB_s2, Cout_AB_s2 => Cout_AB_s2 ); I_RSAgen : RSAgen port map( expAB_s2 => expAB_s2, OPCODE_s2 => OPCODE_s2, rsa => rsa ); I_ROM : ROM port map( addr => addr, x_s1 => x_s1 ); stage1_pipereg : process begin wait until clk = '1'; if reset = '0' then sign_s2 <= '0'; oprA_stat_s2 <= (others => '0'); oprB_stat_s2 <= (others => '0'); OPCODE_s2 <= (others => '0'); expG_s2 <= (others => '0'); expL_s2 <= (others => '0'); fracG_s2 <= (others => '0'); fracL_s2 <= (others => '0'); signA_s2 <= '0'; signB_s2 <= '0'; AgrB_s2 <= '0'; cnt_s2 <= (others => '0'); fracBgteA_s2 <= '0'; x_s2 <= (others => '0'); sel1_MD_s2 <= (others => '0'); sel2_MD_s2 <= (others => '0'); fracA_s2 <= (others => '0'); ALSB_s2 <= '0'; fracB_s2 <= (others => '0'); else if en = '1' then sign_s2 <= sign_s1; oprA_stat_s2 <= oprA_stat_s1; oprB_stat_s2 <= oprB_stat_s1; OPCODE_s2 <= OPCODE_s1; expG_s2 <= expG_s1; expL_s2 <= expL_s1; fracG_s2 <= fracG_s1(30 downto 7); fracL_s2 <= fracL_s1; end if; if en_ALU1 = '1' then signA_s2 <= signA_s1; signB_s2 <= signB_s1; AgrB_s2 <= AgrB; end if; if en_MD1 = '1' then cnt_s2 <= cnt_s1; fracBgteA_s2 <= fracBgteA; x_s2 <= x_s1; sel1_MD_s2 <= sel1_MD_s1; sel2_MD_s2 <= sel2_MD_s1; fracA_s2 <= fracAlsft; ALSB_s2 <= fracA_s1(7); end if; if enB = '1' then fracB_s2 <= fracL_s1(30 downto 7); end if; end if; end process stage1_pipereg; I_stage2_ctrl : stage2_ctrl port map( en => en, OPCODE_s2 => OPCODE_s2, AgrB_s2 => AgrB_s2, fracBgteA_s2 => fracBgteA_s2, oprA_stat_s2 => oprA_stat_s2, oprB_stat_s2 => oprB_stat_s2, cnt_s2 => cnt_s2, oprG_stat_s2 => oprG_stat_s2, oprL_stat_s2 => oprL_stat_s2, fracOPsel => fracOPsel, expCtrl_s2 => expCtrl_s2, en_ALU2 => en_ALU2, en_MD2 => en_MD2, en2_MD => en2_MD ); I_rshift_32b : rshift_32b port map( fracL_s2 => fracL_s2, rsa => rsa, fracLrsh => fracLrsh ); I_sticky_1 : sticky_1 port map( fracL_s2 => fracL_s2, OPCODE_s2 => OPCODE_s2, rsa => rsa, Sticky1 => Sticky1, F2I_IX_s2 => F2I_IX_s2 ); fracLmux <= (sign_s2 & fracLrsh(30 downto 0)) when fracOPsel = '1' else (fracLrsh(31 downto 5) & Sticky1(4 downto 0)); mux3_in <= AddSub2Out_s5(33 downto 1); I_mux3_33b : mux3_33b port map( mux3_in => mux3_in, fracA_s2 => fracA_s2, x_s2 => x_s2, sel1_MD_s2 => sel1_MD_s2, MultIn0 => MultIn0 ); I_mux4_26b : mux4_26b port map( S_fwd => S_fwd, fracL_s2 => fracL_s2, x_s2 => x_s2, fracB_s2 => fracB_s2, sel2_MD_s2 => sel2_MD_s2, MultIn1 => MultIn1 ); stage2_pipereg : process begin wait until clk = '1'; if reset = '0' then sign_s3 <= '0'; oprL_stat_s3 <= (others => '0'); oprG_stat_s3 <= (others => '0'); OPCODE_s3 <= (others => '0'); fracG_MSB_s3 <= '0'; fracL_MSB_s3 <= '0'; signA_s3 <= '0'; signB_s3 <= '0'; expG_s3 <= (others => '0'); fracG_s3 <= (others => '0'); fracAddIn0_s3 <= (others => '0'); F2I_IV_s3 <= '0'; F2I_IX_s3 <= '0'; cnt_s3 <= (others => '0'); expAB_s3 <= (others => '0'); Cout_AB_s3 <= '0'; ALSB_s3 <= '0'; else if en = '1' then sign_s3 <= sign_s2; oprL_stat_s3 <= oprL_stat_s2; oprG_stat_s3 <= oprG_stat_s2; OPCODE_s3 <= OPCODE_s2; fracG_MSB_s3 <= fracG_s2(29); fracL_MSB_s3 <= fracL_s2(29); end if; if en_ALU2 = '1' then signA_s3 <= signA_s2; signB_s3 <= signB_s2; expG_s3 <= expG_s2; fracG_s3 <= fracG_s2; fracAddIn0_s3 <= fracLmux; F2I_IV_s3 <= expAB_s2(8); F2I_IX_s3 <= F2I_IX_s2; end if; if en_MD2 = '1' then cnt_s3 <= cnt_s2; expAB_s3 <= expAB_s2; Cout_AB_s3 <= Cout_AB_s2; ALSB_s3 <= ALSB_s2; end if; end if; end process stage2_pipereg; I_stage3_ctrl : stage3_ctrl port map( en => en, OPCODE_s3 => OPCODE_s3, signA_s3 => signA_s3, signB_s3 => signB_s3, cnt_s3 => cnt_s3, add_ctrl_ALU => add_ctrl_ALU, en_ALU3 => en_ALU3, en_MD3 => en_MD3, en3_MD => en3_MD, enALSB => enALSB ); I_LZ_detect : LZ_detect port map( fracAddOut_s3 => fracAddOut_s3, OPCODE_s3 => OPCODE_s3, oprG_stat_s3 => oprG_stat_s3, oprL_stat_s3 => oprL_stat_s3, fracZero_s3 => fracZero_s3, lz_s3 => lz_s3 ); fracAddin1_s3 <= '0'& fracG_s3 & "0000000"; I_fracAddSub_32b : fracAddSub_32b port map( fracAddIn0_s3 => fracAddIn0_s3, fracAddIn1_s3 => fracAddIn1_s3, add_ctrl_ALU => add_ctrl_ALU, fracAddOut_s3 => fracAddOut_s3 ); I_mult2stage : DW_mult_pipe generic map ( a_width => 33, b_width => 26, num_stages => 2, stall_mode => 1, rst_mode => 2 ) port map ( clk => clk, rst_n => reset, en => en2_MD, tc => '0', a => MultIn0, b => MultIn1, product => MultOut_s3 ); stage3_pipereg : process begin wait until clk = '1'; if reset = '0' then sign_s4 <= '0'; oprG_stat_s4 <= (others => '0'); oprL_stat_s4 <= (others => '0'); OPCODE_s4 <= (others => '0'); fracG_MSB_s4 <= '0'; fracL_MSB_s4 <= '0'; signA_s4 <= '0'; signB_s4 <= '0'; expG_s4 <= (others => '0'); F2I_IV_s4 <= '0'; F2I_IX_s4 <= '0'; fracZero_s4 <= '0'; lz_s4 <= (others => '0'); fracAddOut_s4 <= (others => '0'); cnt_s4 <= (others => '0'); expAB_s4 <= (others => '0'); Cout_AB_s4 <= '0'; MultOut_s4 <= (others => '0'); ALSB_s4 <= '0'; else if en = '1' then sign_s4 <= sign_s3; oprG_stat_s4 <= oprG_stat_s3; oprL_stat_s4 <= oprL_stat_s3; OPCODE_s4 <= OPCODE_s3; fracG_MSB_s4 <= fracG_MSB_s3; fracL_MSB_s4 <= fracL_MSB_s3; end if; if en_ALU3 = '1' then signA_s4 <= signA_s3; signB_s4 <= signB_s3; expG_s4 <= expG_s3; F2I_IV_s4 <= F2I_IV_s3; F2I_IX_s4 <= F2I_IX_s3; fracZero_s4 <= fracZero_s3; lz_s4 <= lz_s3; fracAddOut_s4 <= fracAddOut_s3; end if; if en_MD3 = '1' then cnt_s4 <= cnt_s3; expAB_s4 <= expAB_s3; Cout_AB_s4 <= Cout_AB_s3; end if; if en3_MD = '1' then MultOut_s4 <= MultOut_s3; end if; if enALSB = '1' then ALSB_s4 <= ALSB_s3; end if; end if; end process stage3_pipereg; I_stage4_ctrl : stage4_ctrl port map( en => en, OPCODE_s4 => OPCODE_s4, AddSub2Out => AddSub2Out, lz_s4 => lz_s4, cnt_s4 => cnt_s4, lzOUT => lzOUT, fracRinSEL => fracRinSEL, expCtrl_s4 => expCtrl_s4, sel3_MD => sel3_MD, sel4_MD => sel4_MD, selRin => selRin, add_ctrl_MD => add_ctrl_MD, en_ALU4 => en_ALU4, en_MD4 => en_MD4, en4_MD => en4_MD, enAX => enAX, enQt => enQt, enDiv => enDiv ); I_expBias_9b : expBias_9b port map( expAB_s4 => expAB_s4, expCtrl_s4 => expCtrl_s4, Cout_Bias_s4 => Cout_Bias_s4, expBias_s4 => expBias_s4 ); -- if exp > 00011111 (31) or lz < exp <= 31 then tmpUD = 0 tmpUD_s4 <= '0' when expG_s4 > "00011111" or expG_s4(4 downto 0) > lz_s4 else '1'; -- exp <= lz I_lshift_32b : lshift_32b port map( fracAddOut_s4 => fracAddOut_s4, lz_s4 => lz_s4, fraclsh => fraclsh ); I_sticky_2 : sticky_2 port map( fracAddOut_s4 => fracAddOut_s4, lz_s4 => lz_s4, Sticky2 => Sticky2 ); -- fracRin mux fracRin <= fraclsh when fracRinSEL = '1' else fraclsh(31 downto 5) & Sticky2(4 downto 0); I_tmpIX : tmpIX port map( fracRin => fracRin, tmpIX_s4 => tmpIX_s4 ); -- AddSub1In mux AddSub1In <= "000000" & MultOut_s4(58 downto 31) when sel4_MD = '1' else MultOut_s4(57 downto 24); I_AddSub_1 : AddSub_1 port map( AX => AX, AddSub1In => AddSub1In, add_ctrl_MD => add_ctrl_MD, AddSub1Out => AddSub1Out ); -- multiply result normalization AddSub1OutMux1 <= '0' & AddSub1Out(33 downto 1) when AddSub1Out(33) = '1' else AddSub1Out(33 downto 0); -- pre-round value select : MUL or DIV AddSub1OutMux2 <= AddSub1OutMux1 when sel3_MD = '1' else Qt(33 downto 8) & x"00"; -- pre-round value select : ALU or MULDIV AddSub2In <= AddSub1OutMux2 when selRin = '1' else fracRin & "00"; I_AddSub_2 : AddSub_2 port map( AddSub2In => AddSub2In, add_ctrl_MD => add_ctrl_MD, roundup => roundup, AddSub2Out => AddSub2Out ); I_Round1 : Round1 port map( OPCODE_s4 => OPCODE_s4, fracRin => fracRin, ALSB_s4 => ALSB_s4, MultOut_s4 => MultOut_s4, AddSub1OutMux1 => AddSub1OutMux1, AddSub1OutMux2 => AddSub1OutMux2, ROUND => ROUND, tmpIX_MD_s4 => tmpIX_MD_s4 ); I_Round2 : Round2 port map ( roundup => roundup, OPCODE_s4 => OPCODE_s4, ROUND => ROUND ); stage4_pipereg : process begin wait until clk = '1'; if reset = '0' then OPCODE_s5 <= (others => '0'); signA_s5 <= '0'; signB_s5 <= '0'; expG_s5 <= (others => '0'); F2I_IV_s5 <= '0'; F2I_IX_s5 <= '0'; fracZero_s5 <= '0'; lz_s5 <= (others => '0'); tmpUD_s5 <= '0'; lzLSB_s5 <= '0'; tmpIX_s5 <= '0'; cnt_s5 <= (others => '0'); sign_s5 <= '0'; Cout_AB_s5 <= '0'; Cout_Bias_s5 <= '0'; fracG_MSB_s5 <= '0'; fracL_MSB_s5 <= '0'; oprG_stat_s5 <= (others => '0'); oprL_stat_s5 <= (others => '0'); expBias_s5 <= (others => '0'); AX <= (others => '0'); Qt <= (others => '0'); MultOutMSB_s5 <= '0'; AddSub2Out_s5 <= (others => '0'); tmpIX_MD_s5 <= '0'; else if en = '1' then OPCODE_s5 <= OPCODE_s4; end if; if en_ALU4 = '1' then signA_s5 <= signA_s4; signB_s5 <= signB_s4; expG_s5 <= expG_s4; F2I_IV_s5 <= F2I_IV_s4; F2I_IX_s5 <= F2I_IX_s4; fracZero_s5 <= fracZero_s4; lz_s5 <= lz_s4(4 downto 1) & lzOUT; tmpUD_s5 <= tmpUD_s4; lzLSB_s5 <= lz_s4(0); tmpIX_s5 <= tmpIX_s4; end if; if en_MD4 = '1' then cnt_s5 <= cnt_s4; end if; if enDiv = '1' then sign_s5 <= sign_s4; Cout_AB_s5 <= Cout_AB_s4; Cout_Bias_s5 <= Cout_Bias_s4; fracG_MSB_s5 <= fracG_MSB_s4; fracL_MSB_s5 <= fracL_MSB_s4; oprG_stat_s5 <= oprG_stat_s4; oprL_stat_s5 <= oprL_stat_s4; expBias_s5 <= expBias_s4; end if; if enAX = '1' then AX <= AddSub2Out; end if; if enQt = '1' then Qt <= AddSub2Out(33 downto 8); end if; if en4_MD = '1' then MultOutMSB_s5 <= AddSub1Out(33); AddSub2Out_s5 <= AddSub2Out; tmpIX_MD_s5 <= tmpIX_MD_s4; end if; end if; end process stage4_pipereg; FracMSB <= AddSub2Out_s5(33); I_stage5_ctrl : stage5_ctrl port map( en => en, OPCODE_s5 => OPCODE_s5, AddSub2Out => AddSub2Out, lzLSB_s5 => lzLSB_s5, FracMSB => FracMSB, MultOutMSB_s5 => MultOutMSB_s5, cnt_s5 => cnt_s5, expCtrl_s5 => expCtrl_s5, expIn1sel => expIn1sel, en5_MD => en5_MD ); -- expIN1_s5 mux expIN1_s5 <= expBias_s5 when expIN1sel = '1' else '0' & expG_s5; I_expAddSub_9b_2 : expAddSub_9b_2 port map( expIN1_s5 => expIN1_s5, lz_s5 => lz_s5, expCtrl_s5 => expCtrl_s5, exp_s5 => exp_s5 ); I_EXCEPTION : EXCEPTION port map( OPCODE_s5 => OPCODE_s5, oprG_stat_s5 => oprG_stat_s5, oprL_stat_s5 => oprL_stat_s5, exp_s5 => exp_s5, lzLSB_s5 => lzLSB_s5, F2I_IX_s5 => F2I_IX_s5, Cout_AB_s5 => Cout_AB_s5, Cout_Bias_s5 => Cout_Bias_s5, F2I_IV_s5 => F2I_IV_s5, signA_s5 => signA_s5, signB_s5 => signB_s5, fracG_MSB_s5 => fracG_MSB_s5, fracL_MSB_s5 => fracL_MSB_s5, fracZero_s5 => fracZero_s5, tmpIX_s5 => tmpIX_s5, tmpIX_MD_s5 => tmpIX_MD_s5, tmpUD_s5 => tmpUD_s5, forceInf_I => forceInf_I, D0_flag => D0_flag, IX_flag => IX_flag, IV_flag => IV_flag, OV_flag => OV_flag, UD_flag => UD_flag, forceInf => forceInf, forceNaN => forceNaN, forceUD => forceUD, forceZero => forceZero ); FRAC <= AddSub2Out_s5(33 downto 2); I_ResFormat : ResFormat port map( OPCODE_s5 => OPCODE_s5, sign_s5 => sign_s5, exp_s5 => exp_s5, FRAC => FRAC, forceNaN => forceNaN, forceInf => forceInf, forceUD => forceUD, forceZero => forceZero, forceInf_I => forceInf_I, Result => Result ); Sq_in <= AddSub2Out_s5(25 downto 7); I_Squre : Squre port map( Sq_in => Sq_in, r => r ); Cu_in <= AddSub2Out_s5(25 downto 14); I_Cube : Cube port map( Cu_in => Cu_in, t => t ); I_Accumul : Accumul port map( AddSub2Out_s5 => AddSub2Out_s5, r => r, t => t, S => S ); s_fwd_pipereg : process begin wait until clk = '1'; if reset = '0' then S_fwd <= (others => '0'); else if en5_MD = '1' then S_fwd <= S; end if; end if; end process s_fwd_pipereg; END rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity oprfmta is PORT( OPCODE_s1 : in std_logic_vector(2 downto 0); oprA_s1 : in std_logic_vector(31 downto 0); oprA_stat_s1 : in std_logic_vector(3 downto 0); signA_s1 : out std_logic; expA_s1 : out std_logic_vector(7 downto 0); fracA_s1 : out std_logic_vector(31 downto 0) ); end oprfmta; architecture rtl of oprfmta is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin oprfmta : process (OPCODE_s1, oprA_s1, oprA_stat_s1) variable HIDDEN : std_logic; begin HIDDEN := '0'; case OPCODE_s1 is when OP_I2F => signA_s1 <= oprA_s1(31); expA_s1 <= "00000000"; fracA_s1 <= oprA_s1(31 downto 0); when others => signA_s1 <= oprA_s1(31); expA_s1 <= oprA_s1(30 downto 23); HIDDEN := not(or_reduce(oprA_stat_s1)); fracA_s1 <= '0'& HIDDEN & oprA_s1(22 downto 0) & "0000000"; end case; end process oprfmta; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity oprfmtb is PORT( OPCODE_s1 : in std_logic_vector(2 downto 0); oprB_s1 : in std_logic_vector(31 downto 0); oprB_stat_s1 : in std_logic_vector(3 downto 0); signB_s1 : out std_logic; expB_s1 : out std_logic_vector(7 downto 0); fracB_s1 : out std_logic_vector(31 downto 0) ); end oprfmtb; architecture rtl of oprfmtb is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin oprfmtb : process (OPCODE_s1, oprB_s1, oprB_stat_s1) variable HIDDEN : std_logic; begin HIDDEN := '0'; case OPCODE_s1 is when OP_F2I => signB_s1 <= '0'; expB_s1 <= "10011101"; -- 157 fracB_s1 <= (others => '0'); when OP_I2F => signB_s1 <= '0'; expB_s1 <= "10011101"; -- 157 fracB_s1 <= (others => '0'); when OP_NEG => signB_s1 <= '0'; expB_s1 <= (others => '0'); fracB_s1 <= (others => '0'); when OP_ABS => signB_s1 <= '0'; expB_s1 <= (others => '0'); fracB_s1 <= (others => '0'); when others => signB_s1 <= oprB_s1(31); expB_s1 <= oprB_s1(30 downto 23); HIDDEN := not(or_reduce(oprB_stat_s1)); fracB_s1 <= '0'& HIDDEN & oprB_s1(22 downto 0) & "0000000"; end case; end process oprfmtb; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity count5 is port( clk : in std_logic; en : in std_logic; en_Input : in std_logic; start_Div : in std_logic; OPCODE : in std_logic_vector(2 downto 0); OPCODE_s1 : in std_logic_vector(2 downto 0); cnt_s1 : out std_logic_vector(2 downto 0) ); end count5; architecture rtl of count5 is signal tmp_cnt : std_logic_vector (2 downto 0); constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin count5 : process (clk) begin if (clk'event and clk='1') then if (en = '1') then if (start_Div = '1') then tmp_cnt <= "000"; -- reset count else if (en_Input = '1' and OPCODE /= OP_DIV) then tmp_cnt <= tmp_cnt; -- when incoming OPCODE != OP_DIV else if (OPCODE_s1 = OP_DIV) then -- middle of division if (tmp_cnt = "100") then tmp_cnt <= "000"; -- count from 0 to 4 else tmp_cnt <= tmp_cnt + '1'; -- count only when OP_DIV end if; end if; end if; end if; end if; end if; end process count5; cnt_s1 <= tmp_cnt; end rtl; library ieee; use ieee.std_logic_1164.all; entity comp_31b is port( oprA_s1 : in std_logic_vector(31 downto 0); oprB_s1 : in std_logic_vector(31 downto 0); AeqB : out std_logic; AgrB : out std_logic; fracBgteA : out std_logic ); end comp_31b; architecture rtl of comp_31b is begin comp_31b : process (oprA_s1, oprB_s1) variable expA, expB : std_logic_vector (7 downto 0); variable fracA, fracB : std_logic_vector (22 downto 0); variable expEQ, fracEQ, expAgrB, fracAgrB : std_logic; begin expA := oprA_s1(30 downto 23); expB := oprB_s1(30 downto 23); fracA := oprA_s1(22 downto 0); fracB := oprB_s1(22 downto 0); if (expA = expB) then expEQ := '1'; else expEQ := '0'; end if; if (expA > expB) then expAgrB := '1'; else expAgrB := '0'; end if; if (fracA = fracB) then fracEQ := '1'; else fracEQ := '0'; end if; if (fracA > fracB) then fracAgrB := '1'; else fracAgrB := '0'; end if; AeqB <= expEQ and fracEQ; AgrB <= expAgrB or (expEQ and fracAgrB); fracBgteA <= not(fracAgrB); end process; end rtl; library ieee; use ieee.std_logic_1164.all; entity stage1_ctrl is port( en : in std_logic; OPCODE_s1 : in std_logic_vector(2 downto 0); signA_s1 : in std_logic; signB_s1 : in std_logic; AeqB : in std_logic; AgrB : in std_logic; fracBgteA : in std_logic; cnt_s1 : in std_logic_vector(2 downto 0); Swap : out std_logic; sign_s1 : out std_logic; fracLsft : out std_logic; sel1_MD_s1 : out std_logic_vector(1 downto 0); sel2_MD_s1 : out std_logic_vector(1 downto 0); en_ALU1 : out std_logic; en_MD1 : out std_logic; enB : out std_logic ); end stage1_ctrl; architecture rtl of stage1_ctrl is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin stage1_ctrl : process (en, OPCODE_s1, signA_s1, signB_s1, AeqB, AgrB, fracBgteA, cnt_s1) variable diffsign : std_logic; begin diffsign := signA_s1 xor signB_s1; -- two numbers differ in sign case OPCODE_s1 is when OP_ADD => Swap <= not AgrB; -- choose G/L based on comparator's output if (diffSign = '0') then -- if signs are equal, sign_s1 <= signA_s1 ; -- A's sign will be the sign of the result else if (AeqB = '1') then sign_s1 <= '0'; else if (AgrB = '1') then sign_s1 <= signA_s1; else sign_s1 <= signB_s1; end if; end if; end if; -- A + (-A) : always +0 -- |A| > |B| : signA -- |A| < |B| : signB fracLsft <= '0'; when OP_SUB => Swap <= not AgrB; -- opposite case of ADD instructions if (diffSign = '1') then sign_s1 <= signA_s1 ; else if (AeqB = '1') then sign_s1 <= '0'; else if (AgrB = '1') then sign_s1 <= signA_s1; else sign_s1 <= not signB_s1; end if; end if; end if; fracLsft <= '0'; when OP_F2I => swap <= '1'; sign_s1 <= signA_s1; fracLsft <= '0'; when OP_I2F => swap <= '1'; sign_s1 <= signA_s1; fracLsft <= '0'; when OP_NEG => swap <= '0'; sign_s1 <= not signA_s1 ; -- negate A's sign fracLsft <= '0'; when OP_ABS => swap <= '0'; sign_s1 <= '0'; -- make output sign always positive fracLsft <= '0'; when OP_MUL => swap <= '0'; sign_s1 <= diffsign; fracLsft <= '0'; when OP_DIV => swap <= '0'; sign_s1 <= diffsign; fracLsft <= fracBgteA; when others => null; end case; case OPCODE_s1 is when OP_DIV => case cnt_s1 is when "000" => -- X*B sel1_MD_s1 <= "10"; sel2_MD_s1 <= "01"; when "001" => -- A*X sel1_MD_s1 <= "01"; sel2_MD_s1 <= "10"; when "010" => -- Qt*B sel1_MD_s1 <= "00"; sel2_MD_s1 <= "11"; when "100" => -- A*S sel1_MD_s1 <= "00"; sel2_MD_s1 <= "00"; when others => sel1_MD_s1 <= (others => '0'); -- actually, don't care sel2_MD_s1 <= (others => '0'); -- actually, don't care end case; when others => -- OP_MUL sel1_MD_s1 <= "01"; sel2_MD_s1 <= "01"; end case; if en = '0' then en_ALU1 <= '0'; en_MD1 <= '0'; enB <= '0'; else case OPCODE_s1 is when OP_MUL => en_ALU1 <= '0'; en_MD1 <= '1'; enB <= '0'; when OP_DIV => en_ALU1 <= '0'; en_MD1 <= '1'; case cnt_s1 is when "100" => enB <= '1'; when others => enB <= '0'; end case; when others => en_ALU1 <= '1'; en_MD1 <= '0'; enB <= '0'; end case; end if; end process stage1_ctrl; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity expAddSub_9b_1 is port( expG_s2 : in std_logic_vector(7 downto 0); expL_s2 : in std_logic_vector(7 downto 0); expCtrl_s2 : in std_logic_vector(1 downto 0); expAB_s2 : out std_logic_vector(8 downto 0); Cout_AB_s2 : out std_logic ); end expAddSub_9b_1; architecture rtl of expAddSub_9b_1 is begin expAddSub_9b_1 : process (expG_s2, expL_s2, expCtrl_s2) variable tmp_expAB : std_logic_vector (9 downto 0); variable tmp_expG : std_logic_vector (9 downto 0); variable tmp_expL : std_logic_vector (9 downto 0); variable expL_bar : std_logic_vector (9 downto 0); begin tmp_expG := "00" & expG_s2; tmp_expL := "00" & expL_s2; expL_bar := "01" & not(expL_s2); case expCtrl_s2 is when "00" => tmp_expAB := tmp_expG + expL_bar + "0000000001"; -- expG - expL when "01" => tmp_expAB := tmp_expG + tmp_expL; -- expG + expL when "10" => tmp_expAB := tmp_expG + expL_bar; -- expG - expL - 1 when others => tmp_expAB := tmp_expG + expL_bar + "0000000001"; -- expG - expL end case; Cout_AB_s2 <= tmp_expAB(9) ; expAB_s2 <= tmp_expAB(8 downto 0) ; end process expAddSub_9b_1; end rtl; library ieee; use ieee.std_logic_1164.all; entity RSAgen is port( expAB_s2 : in std_logic_vector(8 downto 0); OPCODE_s2 : in std_logic_vector(2 downto 0); rsa : out std_logic_vector(4 downto 0) ); end RSAgen; architecture rtl of RSAgen is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin RSAgen : process (expAB_s2, OPCODE_s2) begin case OPCODE_s2 is when OP_F2I => if (expAB_s2(8) = '1') then rsa <= "00000"; -- Overflow : No rshift elsif (expAB_s2 > "000011110") then rsa <= "11111"; -- if EXP>30 -> Underflow:set FRAC to 0 -> RSA=31 else rsa <= expAB_s2 (4 downto 0) ; end if; when OP_I2F => rsa <= "00000"; when OP_MUL => rsa <= "00000"; when OP_DIV => rsa <= "00000"; when others => if (expAB_s2 > "000011010") then -- if EXP > 26 rsa <= "11011"; -- set RSA to maximum allowed right shift amount (27) else rsa <= expAB_s2(4 downto 0) ; end if; end case; end process RSAgen; end rtl; library ieee; use ieee.std_logic_1164.all; entity ROM is port( addr : in std_logic_vector(6 downto 0); x_s1 : out std_logic_vector(6 downto 0) ); end ROM; architecture rtl of ROM is begin ROM : process (addr) begin case addr is when "0000000" => x_s1 <= "1111110"; when "0000001" => x_s1 <= "1111100"; when "0000010" => x_s1 <= "1111010"; when "0000011" => x_s1 <= "1111000"; when "0000100" => x_s1 <= "1110110"; when "0000101" => x_s1 <= "1110100"; when "0000110" => x_s1 <= "1110010"; when "0000111" => x_s1 <= "1110000"; when "0001000" => x_s1 <= "1101111"; when "0001001" => x_s1 <= "1101101"; when "0001010" => x_s1 <= "1101011"; when "0001011" => x_s1 <= "1101010"; when "0001100" => x_s1 <= "1101000"; when "0001101" => x_s1 <= "1100110"; when "0001110" => x_s1 <= "1100101"; when "0001111" => x_s1 <= "1100011"; when "0010000" => x_s1 <= "1100001"; when "0010001" => x_s1 <= "1100000"; when "0010010" => x_s1 <= "1011110"; when "0010011" => x_s1 <= "1011101"; when "0010100" => x_s1 <= "1011011"; when "0010101" => x_s1 <= "1011010"; when "0010110" => x_s1 <= "1011001"; when "0010111" => x_s1 <= "1010111"; when "0011000" => x_s1 <= "1010110"; when "0011001" => x_s1 <= "1010100"; when "0011010" => x_s1 <= "1010011"; when "0011011" => x_s1 <= "1010010"; when "0011100" => x_s1 <= "1010000"; when "0011101" => x_s1 <= "1001111"; when "0011110" => x_s1 <= "1001110"; when "0011111" => x_s1 <= "1001100"; when "0100000" => x_s1 <= "1001011"; when "0100001" => x_s1 <= "1001010"; when "0100010" => x_s1 <= "1001001"; when "0100011" => x_s1 <= "1000111"; when "0100100" => x_s1 <= "1000110"; when "0100101" => x_s1 <= "1000101"; when "0100110" => x_s1 <= "1000100"; when "0100111" => x_s1 <= "1000011"; when "0101000" => x_s1 <= "1000001"; when "0101001" => x_s1 <= "1000000"; when "0101010" => x_s1 <= "0111111"; when "0101011" => x_s1 <= "0111110"; when "0101100" => x_s1 <= "0111101"; when "0101101" => x_s1 <= "0111100"; when "0101110" => x_s1 <= "0111011"; when "0101111" => x_s1 <= "0111010"; when "0110000" => x_s1 <= "0111001"; when "0110001" => x_s1 <= "0111000"; when "0110010" => x_s1 <= "0110111"; when "0110011" => x_s1 <= "0110110"; when "0110100" => x_s1 <= "0110101"; when "0110101" => x_s1 <= "0110100"; when "0110110" => x_s1 <= "0110011"; when "0110111" => x_s1 <= "0110010"; when "0111000" => x_s1 <= "0110001"; when "0111001" => x_s1 <= "0110000"; when "0111010" => x_s1 <= "0101111"; when "0111011" => x_s1 <= "0101110"; when "0111100" => x_s1 <= "0101101"; when "0111101" => x_s1 <= "0101100"; when "0111110" => x_s1 <= "0101011"; when "0111111" => x_s1 <= "0101010"; when "1000000" => x_s1 <= "0101001"; when "1000001" => x_s1 <= "0101000"; when "1000010" => x_s1 <= "0101000"; when "1000011" => x_s1 <= "0100111"; when "1000100" => x_s1 <= "0100110"; when "1000101" => x_s1 <= "0100101"; when "1000110" => x_s1 <= "0100100"; when "1000111" => x_s1 <= "0100011"; when "1001000" => x_s1 <= "0100011"; when "1001001" => x_s1 <= "0100010"; when "1001010" => x_s1 <= "0100001"; when "1001011" => x_s1 <= "0100000"; when "1001100" => x_s1 <= "0011111"; when "1001101" => x_s1 <= "0011111"; when "1001110" => x_s1 <= "0011110"; when "1001111" => x_s1 <= "0011101"; when "1010000" => x_s1 <= "0011100"; when "1010001" => x_s1 <= "0011100"; when "1010010" => x_s1 <= "0011011"; when "1010011" => x_s1 <= "0011010"; when "1010100" => x_s1 <= "0011001"; when "1010101" => x_s1 <= "0011001"; when "1010110" => x_s1 <= "0011000"; when "1010111" => x_s1 <= "0010111"; when "1011000" => x_s1 <= "0010111"; when "1011001" => x_s1 <= "0010110"; when "1011010" => x_s1 <= "0010101"; when "1011011" => x_s1 <= "0010100"; when "1011100" => x_s1 <= "0010100"; when "1011101" => x_s1 <= "0010011"; when "1011110" => x_s1 <= "0010010"; when "1011111" => x_s1 <= "0010010"; when "1100000" => x_s1 <= "0010001"; when "1100001" => x_s1 <= "0010000"; when "1100010" => x_s1 <= "0010000"; when "1100011" => x_s1 <= "0001111"; when "1100100" => x_s1 <= "0001111"; when "1100101" => x_s1 <= "0001110"; when "1100110" => x_s1 <= "0001101"; when "1100111" => x_s1 <= "0001101"; when "1101000" => x_s1 <= "0001100"; when "1101001" => x_s1 <= "0001100"; when "1101010" => x_s1 <= "0001011"; when "1101011" => x_s1 <= "0001010"; when "1101100" => x_s1 <= "0001010"; when "1101101" => x_s1 <= "0001001"; when "1101110" => x_s1 <= "0001001"; when "1101111" => x_s1 <= "0001000"; when "1110000" => x_s1 <= "0000111"; when "1110001" => x_s1 <= "0000111"; when "1110010" => x_s1 <= "0000110"; when "1110011" => x_s1 <= "0000110"; when "1110100" => x_s1 <= "0000101"; when "1110101" => x_s1 <= "0000101"; when "1110110" => x_s1 <= "0000100"; when "1110111" => x_s1 <= "0000100"; when "1111000" => x_s1 <= "0000011"; when "1111001" => x_s1 <= "0000011"; when "1111010" => x_s1 <= "0000010"; when "1111011" => x_s1 <= "0000010"; when "1111100" => x_s1 <= "0000001"; when "1111101" => x_s1 <= "0000001"; when "1111110" => x_s1 <= "0000000"; when "1111111" => x_s1 <= "0000000"; when others => null; end case; end process ROM; end rtl; library ieee; use ieee.std_logic_1164.all; entity stage2_ctrl is port( en : in std_logic; OPCODE_s2 : in std_logic_vector(2 downto 0); AgrB_s2 : in std_logic; fracBgteA_s2 : in std_logic; oprA_stat_s2 : in std_logic_vector(3 downto 0); oprB_stat_s2 : in std_logic_vector(3 downto 0); cnt_s2 : in std_logic_vector(2 downto 0); oprG_stat_s2 : out std_logic_vector(3 downto 0); oprL_stat_s2 : out std_logic_vector(3 downto 0); fracOPsel : out std_logic; expCtrl_s2 : out std_logic_vector(1 downto 0); en_ALU2 : out std_logic; en_MD2 : out std_logic; en2_MD : out std_logic ); end stage2_ctrl; architecture rtl of stage2_ctrl is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin stage2_ctrl : process (en, OPCODE_s2, AgrB_s2, fracBgteA_s2, oprA_stat_s2, oprB_stat_s2, cnt_s2) begin case OPCODE_s2 is when OP_ABS | OP_NEG => oprG_stat_s2 <= oprA_stat_s2; oprL_stat_s2 <= "0000"; -- No B input for these instructions, so set to normal fracOPsel <= '0'; when OP_F2I | OP_I2F => oprG_stat_s2 <= "0000"; oprL_stat_s2 <= oprA_stat_s2; fracOPsel <= '1'; when OP_MUL | OP_DIV => oprG_stat_s2 <= oprA_stat_s2; oprL_stat_s2 <= oprB_stat_s2; fracOPsel <= '0'; when others => -- OP_ADD, OP_SUB if AgrB_s2 = '1' then oprG_stat_s2 <= oprA_stat_s2; oprL_stat_s2 <= oprB_stat_s2; else oprG_stat_s2 <= oprB_stat_s2; oprL_stat_s2 <= oprA_stat_s2; end if; fracOPsel <= '0'; end case; case OPCODE_s2 is when OP_MUL => expCtrl_s2 <= "01"; -- expA + expB when OP_DIV => if fracBgteA_s2 = '1' then expCtrl_s2 <= "10"; -- expA - expB - 1 else expCtrl_s2 <= "00"; -- expA - expB end if; when others => expCtrl_s2 <= "00"; -- expA - expB end case; if en = '0' then en_ALU2 <= '0'; en_MD2 <= '0'; en2_MD <= '0'; else case OPCODE_s2 is when OP_MUL => en_ALU2 <= '0'; en_MD2 <= '1'; en2_MD <= '1'; when OP_DIV=> en_ALU2 <= '0'; en_MD2 <= '1'; case cnt_s2 is when "000" => en2_MD <= '1'; when "001" => en2_MD <= '1'; when "010" => en2_MD <= '1'; when "011" => en2_MD <= '0'; when "100" => en2_MD <= '1'; when others => en2_MD <= '0'; end case; when others => en_ALU2 <= '1'; en_MD2 <= '0'; en2_MD <= '0'; end case; end if; end process stage2_ctrl; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity rshift_32b is port( fracL_s2 : in std_logic_vector(31 downto 0); rsa : in std_logic_vector(4 downto 0); fracLrsh : out std_logic_vector(31 downto 0) ); end rshift_32b; architecture rtl of rshift_32b is begin fracLrsh <= conv_std_logic_vector(shr(unsigned(fracL_s2),unsigned(rsa)),32); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity sticky_1 is port( fracL_s2 : in std_logic_vector(31 downto 0); OPCODE_s2 : in std_logic_vector(2 downto 0); rsa : in std_logic_vector(4 downto 0); Sticky1 : out std_logic_vector(4 downto 0); F2I_IX_s2 : out std_logic ); end sticky_1; architecture rtl of sticky_1 is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin sticky_1 : process (fracL_s2,OPCODE_s2,rsa) variable tmpSticky : std_logic; begin tmpSticky := '0'; case OPCODE_s2 is when OP_F2I => Sticky1 <= "00000"; case rsa is when "01000" => F2I_IX_s2 <= fracL_s2(7); when "01001" => F2I_IX_s2 <= or_reduce(fracL_s2(8 downto 7)); when "01010" => F2I_IX_s2 <= or_reduce(fracL_s2(9 downto 7)); when "01011" => F2I_IX_s2 <= or_reduce(fracL_s2(10 downto 7)); when "01100" => F2I_IX_s2 <= or_reduce(fracL_s2(11 downto 7)); when "01101" => F2I_IX_s2 <= or_reduce(fracL_s2(12 downto 7)); when "01110" => F2I_IX_s2 <= or_reduce(fracL_s2(13 downto 7)); when "01111" => F2I_IX_s2 <= or_reduce(fracL_s2(14 downto 7)); when "10000" => F2I_IX_s2 <= or_reduce(fracL_s2(15 downto 7)); when "10001" => F2I_IX_s2 <= or_reduce(fracL_s2(16 downto 7)); when "10010" => F2I_IX_s2 <= or_reduce(fracL_s2(17 downto 7)); when "10011" => F2I_IX_s2 <= or_reduce(fracL_s2(18 downto 7)); when "10100" => F2I_IX_s2 <= or_reduce(fracL_s2(19 downto 7)); when "10101" => F2I_IX_s2 <= or_reduce(fracL_s2(20 downto 7)); when "10110" => F2I_IX_s2 <= or_reduce(fracL_s2(21 downto 7)); when "10111" => F2I_IX_s2 <= or_reduce(fracL_s2(22 downto 7)); when "11000" => F2I_IX_s2 <= or_reduce(fracL_s2(23 downto 7)); when "11001" => F2I_IX_s2 <= or_reduce(fracL_s2(24 downto 7)); when "11010" => F2I_IX_s2 <= or_reduce(fracL_s2(25 downto 7)); when "11011" => F2I_IX_s2 <= or_reduce(fracL_s2(26 downto 7)); when "11100" => F2I_IX_s2 <= or_reduce(fracL_s2(27 downto 7)); when "11101" => F2I_IX_s2 <= or_reduce(fracL_s2(28 downto 7)); when "11110" => F2I_IX_s2 <= or_reduce(fracL_s2(29 downto 7)); when "11111" => F2I_IX_s2 <= or_reduce(fracL_s2(30 downto 7)); when others => F2I_IX_s2 <= '0'; end case; when others => case rsa is when "00011" => tmpSticky := fracL_s2(7); when "00100" => tmpSticky := or_reduce(fracL_s2(8 downto 7)); when "00101" => tmpSticky := or_reduce(fracL_s2(9 downto 7)); when "00110" => tmpSticky := or_reduce(fracL_s2(10 downto 7)); when "00111" => tmpSticky := or_reduce(fracL_s2(11 downto 7)); when "01000" => tmpSticky := or_reduce(fracL_s2(12 downto 7)); when "01001" => tmpSticky := or_reduce(fracL_s2(13 downto 7)); when "01010" => tmpSticky := or_reduce(fracL_s2(14 downto 7)); when "01011" => tmpSticky := or_reduce(fracL_s2(15 downto 7)); when "01100" => tmpSticky := or_reduce(fracL_s2(16 downto 7)); when "01101" => tmpSticky := or_reduce(fracL_s2(17 downto 7)); when "01110" => tmpSticky := or_reduce(fracL_s2(18 downto 7)); when "01111" => tmpSticky := or_reduce(fracL_s2(19 downto 7)); when "10000" => tmpSticky := or_reduce(fracL_s2(20 downto 7)); when "10001" => tmpSticky := or_reduce(fracL_s2(21 downto 7)); when "10010" => tmpSticky := or_reduce(fracL_s2(22 downto 7)); when "10011" => tmpSticky := or_reduce(fracL_s2(23 downto 7)); when "10100" => tmpSticky := or_reduce(fracL_s2(24 downto 7)); when "10101" => tmpSticky := or_reduce(fracL_s2(25 downto 7)); when "10110" => tmpSticky := or_reduce(fracL_s2(26 downto 7)); when "10111" => tmpSticky := or_reduce(fracL_s2(27 downto 7)); when "11000" => tmpSticky := or_reduce(fracL_s2(28 downto 7)); when "11001" => tmpSticky := or_reduce(fracL_s2(29 downto 7)); when "11010" => tmpSticky := or_reduce(fracL_s2(30 downto 7)); when "11011" => tmpSticky := or_reduce(fracL_s2(30 downto 7)); when others => tmpSticky := '0'; end case; Sticky1 <= tmpSticky & "0000"; F2I_IX_s2 <= '0'; end case; end process sticky_1; end rtl; library ieee; use ieee.std_logic_1164.all; entity mux3_33b is port( mux3_in : in std_logic_vector(32 downto 0); fracA_s2 : in std_logic_vector(24 downto 0); x_s2 : in std_logic_vector(6 downto 0); sel1_MD_s2 : in std_logic_vector(1 downto 0); MultIn0 : out std_logic_vector(32 downto 0) ); end mux3_33b; architecture rtl of mux3_33b is begin mux3_33b : process (mux3_in, fracA_s2, x_s2, sel1_MD_s2) variable IN1 : std_logic_vector(32 downto 0); variable IN2 : std_logic_vector(32 downto 0); begin IN1 := fracA_s2 & x"00"; IN2 := "00" & '1' & x_s2 & "000" & x"00000"; case sel1_MD_s2 is when "00" => MultIn0 <= mux3_in; -- S, AX, Qt when "01" => MultIn0 <= IN1; -- A when "10" => MultIn0 <= IN2; -- X when others => MultIn0 <= (others => '0'); -- actually, don't care end case; end process mux3_33b; end rtl; library ieee; use ieee.std_logic_1164.all; entity mux4_26b is port( S_fwd : in std_logic_vector(25 downto 0); fracL_s2 : in std_logic_vector(31 downto 0); x_s2 : in std_logic_vector(6 downto 0); fracB_s2 : in std_logic_vector(30 downto 7); sel2_MD_s2 : in std_logic_vector(1 downto 0); MultIn1 : out std_logic_vector(25 downto 0) ); end mux4_26b; architecture rtl of mux4_26b is begin mux4_26b : process (S_fwd, fracL_s2, x_s2, fracB_s2, sel2_MD_s2) variable IN0 : std_logic_vector(25 downto 0); variable IN1 : std_logic_vector(25 downto 0); variable IN2 : std_logic_vector(25 downto 0); variable IN3 : std_logic_vector(25 downto 0); begin In0 := S_fwd; IN1 := fracL_s2(30 downto 7) & "00"; IN2 := '0' & '1' & x_s2 & '0' & x"0000"; IN3 := fracB_s2(30 downto 7) & "00"; case sel2_MD_s2 is when "00" => MultIn1 <= IN0; when "01" => MultIn1 <= IN1; when "10" => MultIn1 <= IN2; when "11" => MultIn1 <= IN3; when others => null; end case; end process mux4_26b; end rtl; library ieee; use ieee.std_logic_1164.all; entity stage3_ctrl is port( en : in std_logic; OPCODE_s3 : in std_logic_vector(2 downto 0); signA_s3 : in std_logic; signB_s3 : in std_logic; cnt_s3 : in std_logic_vector(2 downto 0); add_ctrl_ALU : out std_logic_vector(1 downto 0); en_ALU3 : out std_logic; en_MD3 : out std_logic; en3_MD : out std_logic; enALSB : out std_logic ); end stage3_ctrl; architecture rtl of stage3_ctrl is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin stage3_ctrl : process (en, OPCODE_s3, signA_s3, signB_s3, cnt_s3) variable diffsign : std_logic; begin diffsign := signA_s3 xor signB_s3; case OPCODE_s3 is when OP_ADD => add_ctrl_ALU <= '0' & diffSign; -- (+) - (+) -> ADD -- (-) - (-) -> ADD -- (+) - (-) -> SUB -- (-) - (+) -> SUB when OP_SUB => add_ctrl_ALU <= '0' & not diffSign; -- (+) - (+) -> SUB -- (-) - (-) -> SUB -- (+) - (-) -> ADD -- (-) - (+) -> ADD when OP_F2I => -- convert 2's complement to signed magnitude if (signA_s3 = '1') then add_ctrl_ALU <= "10"; else add_ctrl_ALU <= "00"; end if; when OP_I2F => -- convert 2's complement to signed magnitude if (signa_s3 = '1') then add_ctrl_ALU <= "10"; else add_ctrl_ALU <= "00"; end if; when others => add_ctrl_ALU <= '0' & diffSign; -- OP_ABS & OP_NEG : B's sign = 0 and fraction is zero.. -- so doesn't matter end case; if en = '0' then en_ALU3 <= '0'; en_MD3 <= '0'; en3_MD <= '0'; enALSB <= '0'; else case OPCODE_s3 is when OP_MUL => en_ALU3 <= '0'; en_MD3 <= '1'; en3_MD <= '1'; enALSB <= '0'; when OP_DIV => en_ALU3 <= '0'; en_MD3 <= '1'; case cnt_s3 is when "000" => en3_MD <= '1'; enALSB <= '0'; when "001" => en3_MD <= '1'; enALSB <= '0'; when "010" => en3_MD <= '1'; enALSB <= '0'; when "011" => en3_MD <= '0'; enALSB <= '1'; when "100" => en3_MD <= '1'; enALSB <= '0'; when others => en3_MD <= '0'; enALSB <= '0'; end case; when others => en_ALU3 <= '1'; en_MD3 <= '0'; en3_MD <= '0'; enALSB <= '0'; end case; end if; end process stage3_ctrl; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity LZ_detect is port( fracAddOut_s3 : in std_logic_vector(31 downto 0); OPCODE_s3 : in std_logic_vector(2 downto 0); oprG_stat_s3 : in std_logic_vector(3 downto 0); oprL_stat_s3 : in std_logic_vector(3 downto 0); fracZero_s3 : out std_logic; lz_s3 : out std_logic_vector(4 downto 0) ); end LZ_detect; architecture rtl of LZ_detect is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin LZ_detect : process (fracAddOut_s3,OPCODE_s3,oprG_stat_s3,oprL_stat_s3) variable tmpOUT : std_logic_vector (4 downto 0); variable EXCEP : std_logic; begin if (OPCODE_s3 = OP_ADD) or (OPCODE_s3 = OP_SUB) or (OPCODE_s3 = OP_F2I) then if (or_reduce(oprG_stat_s3(2 downto 0)) = '1') or (or_reduce(oprL_stat_s3(2 downto 0)) = '1') then -- Zero, Inf, NaN EXCEP := '1'; else EXCEP := '0'; end if; else EXCEP := '0'; end if; case OPCODE_s3 is when OP_ABS => tmpOUT := "00000"; when OP_NEG => tmpOUT := "00000"; when OP_F2I => tmpOUT := "00000"; when others => if (EXCEP = '1') then -- either of one is Zero, Inf, NaN tmpOUT := "00000"; else if (fracAddOut_s3(31) = '1') then tmpOUT := "00000"; elsif (fracAddOut_s3(31 downto 30) = "01") then tmpOUT := "00000"; elsif (fracAddOut_s3(31 downto 29) = "001") then tmpOUT := "00001"; elsif (fracAddOut_s3(31 downto 28) = "0001") then tmpOUT := "00010"; elsif (fracAddOut_s3(31 downto 27) = "00001") then tmpOUT := "00011"; elsif (fracAddOut_s3(31 downto 26) = "000001") then tmpOUT := "00100"; elsif (fracAddOut_s3(31 downto 25) = "0000001") then tmpOUT := "00101"; elsif (fracAddOut_s3(31 downto 24) = "00000001") then tmpOUT := "00110"; elsif (fracAddOut_s3(31 downto 23) = "000000001") then tmpOUT := "00111"; elsif (fracAddOut_s3(31 downto 22) = "0000000001") then tmpOUT := "01000"; elsif (fracAddOut_s3(31 downto 21) = "00000000001") then tmpOUT := "01001"; elsif (fracAddOut_s3(31 downto 20) = "000000000001") then tmpOUT := "01010"; elsif (fracAddOut_s3(31 downto 19) = "0000000000001") then tmpOUT := "01011"; elsif (fracAddOut_s3(31 downto 18) = "00000000000001") then tmpOUT := "01100"; elsif (fracAddOut_s3(31 downto 17) = "000000000000001") then tmpOUT := "01101"; elsif (fracAddOut_s3(31 downto 16) = "0000000000000001") then tmpOUT := "01110"; elsif (fracAddOut_s3(31 downto 15) = "00000000000000001") then tmpOUT := "01111"; elsif (fracAddOut_s3(31 downto 14) = "000000000000000001") then tmpOUT := "10000"; elsif (fracAddOut_s3(31 downto 13) = "0000000000000000001") then tmpOUT := "10001"; elsif (fracAddOut_s3(31 downto 12) = "00000000000000000001") then tmpOUT := "10010"; elsif (fracAddOut_s3(31 downto 11) = "000000000000000000001") then tmpOUT := "10011"; elsif (fracAddOut_s3(31 downto 10) = "0000000000000000000001") then tmpOUT := "10100"; elsif (fracAddOut_s3(31 downto 9) = "00000000000000000000001") then tmpOUT := "10101"; elsif (fracAddOut_s3(31 downto 8) = "000000000000000000000001") then tmpOUT := "10110"; elsif (fracAddOut_s3(31 downto 7) = "0000000000000000000000001") then tmpOUT := "10111"; elsif (fracAddOut_s3(31 downto 6) = "00000000000000000000000001") then tmpOUT := "11000"; elsif (fracAddOut_s3(31 downto 5) = "000000000000000000000000001") then tmpOUT := "11001"; elsif (fracAddOut_s3(31 downto 4) = "0000000000000000000000000001") then tmpOUT := "11010"; elsif (fracAddOut_s3(31 downto 3) = "00000000000000000000000000001") then tmpOUT := "11011"; elsif (fracAddOut_s3(31 downto 2) = "000000000000000000000000000001") then tmpOUT := "11100"; elsif (fracAddOut_s3(31 downto 1) = "0000000000000000000000000000001") then tmpOUT := "11101"; elsif (fracAddOut_s3(31 downto 0) = "00000000000000000000000000000001") then tmpOUT := "11110"; else tmpOUT := "11111"; end if; end if; end case; case OPCODE_s3 is when OP_I2F => if (tmpOUT = "11111") then fracZero_s3 <= '1'; else fracZero_s3 <= '0'; end if; when others => if (tmpOUT > "11010") then fracZero_s3 <= '1'; else fracZero_s3 <= '0'; end if; end case; lz_s3 <= tmpOUT ; end process LZ_detect; end rtl; library ieee, synopsys; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use synopsys.attributes.all; entity fracAddSub_32b is port( fracAddIn0_s3 : in std_logic_vector(31 downto 0); fracAddIn1_s3 : in std_logic_vector(31 downto 0); add_ctrl_ALU : in std_logic_vector(1 downto 0); fracAddOut_s3 : out std_logic_vector(31 downto 0) ); end fracAddSub_32b; architecture rtl of fracAddSub_32b is begin fracAddSub_32b : process (fracAddIn0_s3,fracAddIn1_s3,add_ctrl_ALU) constant ADD : std_logic_vector (1 downto 0) := "00"; constant SUB : std_logic_vector (1 downto 0) := "01"; constant CON : std_logic_vector (1 downto 0) := "10"; constant r0 : resource := 0; attribute map_to_module of r0: constant is "DW01_addsub"; attribute implementation of r0: constant is "pparch"; attribute ops of r0: constant is "a1 a2 a3 a4"; begin case add_ctrl_ALU is when ADD => fracAddOut_s3 <= fracAddIn1_s3 + fracAddIn0_s3; -- pragma label a1 when SUB => fracAddOut_s3 <= fracAddIn1_s3 - fracAddIn0_s3; -- pragma label a2 when CON => fracAddOut_s3 <= '1' + (not fracAddIn0_s3); -- pragma label a3 when others => fracAddOut_s3 <= fracAddIn1_s3 + fracAddIn0_s3; -- pragma label a4 end case; end process fracAddSub_32b; end rtl; library ieee; use ieee.std_logic_1164.all; entity stage4_ctrl is port( en : in std_logic; OPCODE_s4 : in std_logic_vector(2 downto 0); AddSub2Out : in std_logic_vector(33 downto 0); lz_s4 : in std_logic_vector(4 downto 0); cnt_s4 : in std_logic_vector(2 downto 0); lzOUT : out std_logic; fracRinSEL : out std_logic; expCtrl_s4 : out std_logic; sel3_MD : out std_logic; sel4_MD : out std_logic; selRin : out std_logic; add_ctrl_MD : out std_logic_vector(1 downto 0); en_ALU4 : out std_logic; en_MD4 : out std_logic; en4_MD : out std_logic; enAX : out std_logic; enQt : out std_logic; enDiv : out std_logic ); end stage4_ctrl; architecture rtl of stage4_ctrl is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin stage4_ctrl : process (en, OPCODE_s4, AddSub2Out, lz_s4, cnt_s4) begin case OPCODE_s4 is when OP_NEG => lzOUT <= lz_s4(0); fracRinSEL <= '0'; when OP_ABS => lzOUT <= lz_s4(0); fracRinSEL <= '0'; when OP_F2I => lzOUT <= lz_s4(0); fracRinSEL <= '1'; when others => if ADdSub2Out(33 downto 32) = "10" then lzOUT <= '0'; else lzOUT <= lz_s4(0); end if; fracRinSEL <= '0'; end case; case OPCODE_s4 is when OP_MUL => expCtrl_s4 <= '0'; when OP_DIV => expCtrl_s4 <= '1'; when others => expCtrl_s4 <= '0'; end case; case OPCODE_s4 is when OP_MUL => sel3_MD <= '1'; sel4_MD <= '0'; selRin <= '1'; add_ctrl_MD <= "11"; when OP_DIV => selRin <= '1'; case cnt_s4 is when "000" => sel3_MD <= '1'; sel4_MD <= '0'; add_ctrl_MD <= "01"; when "001" => sel3_MD <= '1'; sel4_MD <= '0'; add_ctrl_MD <= "00"; when "010" => sel3_MD <= '0'; sel4_MD <= '0'; add_ctrl_MD <= "11"; when "100" => sel3_MD <= '1'; sel4_MD <= '1'; add_ctrl_MD <= "10"; when others => sel3_MD <= '0'; -- don't care sel4_MD <= '0'; -- don't care add_ctrl_MD <= "00"; -- don't care end case; when others => sel3_MD <= '0'; -- don't care sel4_MD <= '0'; -- don't care selRin <= '0'; add_ctrl_MD <= "11"; end case; if en = '0' then en_ALU4 <= '0'; en_MD4 <= '0'; en4_MD <= '0'; enAX <= '0'; enQt <= '0'; enDiv <= '0'; else case OPCODE_s4 is when OP_MUL => en_ALU4 <= '0'; en_MD4 <= '1'; en4_MD <= '1'; enAX <= '0'; enQt <= '0'; enDiv <= '1'; when OP_DIV => en_ALU4 <= '0'; en_MD4 <= '1'; case cnt_s4 is when "000" => en4_MD <= '1'; enAX <= '0'; enQt <= '0'; enDiv <= '0'; when "001" => en4_MD <= '1'; enAX <= '1'; enQt <= '0'; enDiv <= '0'; when "010" => en4_MD <= '1'; enAX <= '0'; enQt <= '0'; enDiv <= '0'; when "011" => en4_MD <= '0'; enAX <= '0'; enQt <= '0'; enDiv <= '1'; when "100" => en4_MD <= '1'; enAX <= '0'; enQt <= '1'; enDiv <= '0'; when others => en4_MD <= '0'; enAX <= '0'; enQt <= '0'; enDiv <= '0'; end case; when others => en_ALU4 <= '1'; en_MD4 <= '0'; en4_MD <= '1'; enAX <= '0'; enQt <= '0'; enDiv <= '1'; end case; end if; end process stage4_ctrl; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity expBias_9b is port( expAB_s4 : in std_logic_vector(8 downto 0); expCtrl_s4 : in std_logic; Cout_Bias_s4 : out std_logic; expBias_s4 : out std_logic_vector(8 downto 0) ); end expBias_9b; architecture rtl of expBias_9b is begin expBias_9b : process (expAB_s4, expCtrl_s4) variable tmp : std_logic_vector (9 downto 0); begin if expCtrl_s4 = '0' then tmp := '0'& expAB_s4 + "110000001"; -- expA + expB - 157 else tmp := '0'& expAB_s4 + "001111111"; -- expA - expB + 157 end if; Cout_Bias_s4 <= tmp(9); expBias_s4 <= tmp(8 downto 0); end process expBias_9b; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity lshift_32b is port( fracAddOut_s4 : in std_logic_vector(31 downto 0); lz_s4 : in std_logic_vector(4 downto 0); fraclsh : out std_logic_vector(31 downto 0) ); end lshift_32b; architecture rtl of lshift_32b is begin fraclsh <= conv_std_logic_vector(shl(unsigned(fracAddOut_s4),unsigned(lz_s4)),32); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity sticky_2 is port( fracAddOut_s4 : in std_logic_vector(31 downto 0); lz_s4 : in std_logic_vector(4 downto 0); Sticky2 : out std_logic_vector(4 downto 0) ); end sticky_2; architecture rtl of sticky_2 is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin sticky_2 : process (fracAddOut_s4,lz_s4) begin case lz_s4 is when "00000" => Sticky2 <= or_reduce(fracAddOut_s4(4 downto 0)) & "0000"; when "00001" => Sticky2 <= or_reduce(fracAddOut_s4(3 downto 0)) & "0000"; when "00010" => Sticky2 <= or_reduce(fracAddOut_s4(2 downto 0)) & "0000"; when "00011" => Sticky2 <= or_reduce(fracAddOut_s4(1 downto 0)) & "0000"; when "00100" => Sticky2 <= fracAddOut_s4(0) & "0000"; when others => Sticky2 <= "00000"; end case; end process sticky_2; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity tmpIX is port( fracRin : in std_logic_vector(31 downto 0); tmpIX_s4 : out std_logic ); end tmpIX; architecture rtl of tmpIX is begin tmpIX : process (fracRin) begin if (fracRin(31) = '1') then -- 1x.xxxx.... if ((fracRin(7) or fracRin(6) or fracRin(5) or fracRin(4)) = '1') then tmpIX_s4 <= '1'; else tmpIX_s4 <= '0'; end if; elsif ((fracRin(6) or fracRin(5) or fracRin(4)) = '1') then -- 0x.xxxx.... tmpIX_s4 <= '1'; else tmpIX_s4 <= '0'; end if; end process tmpIX; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity AddSub_1 is port( AX : in std_logic_vector(33 downto 0); AddSub1In : in std_logic_vector(33 downto 0); add_ctrl_MD : in std_logic_vector(1 downto 0); AddSub1Out : out std_logic_vector(33 downto 0) ); end AddSub_1; architecture rtl of AddSub_1 is begin AddSub_1 : process (AX, AddSub1In, add_ctrl_MD) constant Pass : std_logic_vector (1 downto 0) := "00"; constant MinusBX : std_logic_vector (1 downto 0) := "01"; constant Qt : std_logic_vector (1 downto 0) := "10"; constant Round : std_logic_vector (1 downto 0) := "11"; begin case add_ctrl_MD is when Pass => AddSub1Out <= AddSub1In; when MinusBX => AddSub1Out <= AddSub1In; when Qt => AddSub1Out <= AX + AddSub1In; when Round => AddSub1Out <= AddSub1In; when others => null; end case; end process AddSub_1; end rtl; library ieee, synopsys; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use synopsys.attributes.all; entity AddSub_2 is port( AddSub2In : in std_logic_vector(33 downto 0); add_ctrl_MD : in std_logic_vector(1 downto 0); roundup : in std_logic; AddSub2Out : out std_logic_vector(33 downto 0) ); end AddSub_2; architecture rtl of AddSub_2 is begin AddSub_2 : process (AddSub2In, add_ctrl_MD, roundup) constant Pass : std_logic_vector (1 downto 0) := "00"; constant MinusBX : std_logic_vector (1 downto 0) := "01"; constant Qt : std_logic_vector (1 downto 0) := "10"; constant Round : std_logic_vector (1 downto 0) := "11"; constant r0 : resource := 0; attribute map_to_module of r0: constant is "DW01_addsub"; attribute implementation of r0: constant is "pparch"; attribute ops of r0: constant is "a1 a2 a3"; begin case add_ctrl_MD is when Pass => AddSub2Out <= AddSub2In; when MinusBX => AddSub2Out <= "0100000000000000000000000000000000" - AddSub2In; -- pragma label a1 when Qt => AddSub2Out <= "0000000000000000000000000100000000" + (AddSub2In(33 downto 8) & "00000000"); -- pragma label a2 when Round => if roundup = '1' then AddSub2Out <= "0000000000000000000000001000000000" + AddSub2In; -- pragma label a3 else AddSub2Out <= AddSub2In; end if; when others => null; end case; end process AddSub_2; -- MinusBX = 33'h100000000 - AddSub2In -- Qt = 256 + {AddSub2In[33:8],8'h00} -- round = 512 + AddSub2In end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity Round1 is port( OPCODE_s4 : in std_logic_vector(2 downto 0); fracRin : in std_logic_vector(31 DOWNTO 0); ALSB_s4 : in std_logic; MultOut_s4 : in std_logic_vector(58 DOWNTO 0); AddSub1OutMux1 : in std_logic_vector(33 DOWNTO 0); AddSub1OutMux2 : in std_logic_vector(33 DOWNTO 0); ROUND : out std_logic_vector(3 downto 0); tmpIX_MD_s4 : out std_logic ); end Round1; architecture rtl of Round1 is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin round1 : process (OPCODE_s4, fracRin, ALSB_s4, MultOut_s4, AddSub1OutMux1, AddSub1OutMux2) variable MLGRS : std_logic_vector (5 downto 0); variable QtG : std_logic; variable QtB1 : std_logic_vector (23 downto 0); variable QtB2 : std_logic_vector (9 downto 0); variable sticky : std_logic; begin MLGRS := fracRin(31) & fracRin(8 downto 4); QtG := AddSub1OutMux2(8); QtB1 := MultOut_s4(23 downto 0); QtB2 := AddSub1OutMux1(9 downto 0); sticky := '0'; case OPCODE_s4 is when OP_NEG | OP_ABS | OP_F2I => ROUND <= (others => '0'); tmpIX_MD_s4 <= '0'; when OP_MUL => ROUND <= QtB2(9 downto 7) & (or_reduce(QtB2(6 downto 0)) or or_reduce(QtB1(23 downto 0))); if (or_reduce(QtB2(8 downto 0)) or or_reduce(QtB1(23 downto 0))) = '1' then tmpIX_MD_s4 <= '1'; else tmpIX_MD_s4 <= '0'; end if; when OP_DIV => sticky := or_reduce(QtB1(23 downto 0)) or or_reduce(QtB2(8 downto 0)); if (QtG='1') and (sticky='1') and (ALSB_s4 /= QtB2(9)) then ROUND <= "1111"; else ROUND <= "0000"; end if; tmpIX_MD_s4 <= '0'; when others => if (MLGRS(5) = '1') then -- fracLSH = 1x.xxxx ROUND <= MLGRS(4 downto 2) & or_reduce(MLGRS(1 downto 0)); else -- fracLSH = 01.xxxx ROUND <= MLGRS(3 downto 0); end if; tmpIX_MD_s4 <= '0'; end case; end process round1; end rtl; library ieee; use ieee.std_logic_1164.all; entity Round2 is port( roundup : out std_logic; OPCODE_s4 : in std_logic_vector(2 downto 0); ROUND : in std_logic_vector(3 downto 0) ); end Round2; architecture rtl of Round2 is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin round2 : process (ROUND, OPCODE_s4) begin case OPCODE_s4 is when OP_NEG | OP_ABS | OP_F2I => roundup <= '0'; when others => roundup <= ROUND(2) and (ROUND(3) or ROUND(1) or ROUND(0)); -- ROUNDUP = LG + GS + GR = G(L + R + S) end case; end process round2; end rtl; library ieee; use ieee.std_logic_1164.all; entity stage5_ctrl is port( en : in std_logic; OPCODE_s5 : in std_logic_vector(2 downto 0); AddSub2Out : in std_logic_vector(33 downto 0); lzLSB_s5 : in std_logic; FracMSB : in std_logic; MultOutMSB_s5 : in std_logic; cnt_s5 : in std_logic_vector(2 downto 0); expCtrl_s5 : out std_logic_vector(1 downto 0); expIn1sel : out std_logic; en5_MD : out std_logic ); end stage5_ctrl; architecture rtl of stage5_ctrl is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin stage5_ctrl : process (en, OPCODE_s5, lzLSB_s5, FracMSB, MultOutMSB_s5, cnt_s5) begin case OPCODE_s5 is when OP_MUL => if (MultOutMSB_s5 or FracMSB) = '1' then expCtrl_s5 <= "10"; else expCtrl_s5 <= "11"; end if; expIN1sel <= '1'; when OP_DIV => if FracMSB = '1' then expCtrl_s5 <= "10"; else expCtrl_s5 <= "11"; end if; expIN1sel <= '1'; when others => expIN1sel <= '0'; if (FracMSB = '0') then -- Frac = 0x.xxxx.... expCtrl_s5 <= "00" ; -- exp = exp - lz else -- Frac = 1x.xxxx.... if (lzLSB_s5 = '1') then expCtrl_s5 <= "00"; -- exp = exp - 0 else expCtrl_s5 <= "01"; -- exp = exp + 0 + 1 end if; end if; end case; if en = '0' then en5_MD <= '0'; else case OPCODE_s5 is when OP_DIV => case cnt_s5 is when "000" => en5_MD <= '1'; when "010" => en5_MD <= '0'; when others => en5_MD <= '0'; end case; when others => en5_MD <= '0'; end case; end if; end process stage5_ctrl; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity expAddSub_9b_2 is port( expIN1_s5 : in std_logic_vector(8 downto 0); lz_s5 : in std_logic_vector(4 downto 0); expCtrl_s5 : in std_logic_vector(1 downto 0); exp_s5 : out std_logic_vector(8 downto 0) ); end expAddSub_9b_2; architecture rtl of expAddSub_9b_2 is begin expAddSub_9b_2 : process (expIN1_s5, lz_s5, expCtrl_s5) variable IN0 : std_logic_vector (8 downto 0); begin IN0 := "0000" & lz_s5; case expCtrl_s5 is when "00" => exp_s5 <= expIN1_s5 - IN0; when "01" => exp_s5 <= expIN1_s5 + IN0 + '1'; when "10" => exp_s5 <= expIN1_s5 + '1'; when "11" => exp_s5 <= expIN1_s5; when others => null; end case; end process expAddSub_9b_2; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity Squre is port( Sq_in : in std_logic_vector(24 downto 6); r : out std_logic_vector(19 downto 1) ); end Squre; architecture rtl of Squre is begin Squre : process (Sq_in) variable s01, s02, s03, s04, s05, s06, s07, s08, s09, s10 : std_logic; variable s11, s12, s13, s14, s15, s16, s17, s18, s19, s20 : std_logic; variable s21, s22, s23, s24, s25, s26, s27, s28, s29, s30 : std_logic; variable s31, s32, s33, s34, s35, s36, s37, s38, s39, s40 : std_logic; variable s41, s42, s43, s44, s45, s46, s47, s48, s49, s50 : std_logic; variable s51, s52, s53, s54, s55, s56, s57, s58, s59, s60 : std_logic; variable s61, s62, s63, s64, s65, s66, s67, s68, s69, s70 : std_logic; variable s71, s72, s73, s74, s75, s76, s77, s78, s79, s80 : std_logic; variable s81, s82, s83, s84, s85, s86, s87, s88, s89, s90 : std_logic; variable r01, r02, r03, r04, r05, r06, r07, r08, r09, r10 : std_logic_vector (19 downto 1); variable r11, r12, r13, r14, r15, r16, r17, r18, r19, r20 : std_logic_vector (19 downto 1); variable r21, r22, r23, r24, r25, r26, r27, r28, r29, r30 : std_logic_vector (19 downto 1); variable r31, r32, r33, r34, r35, r36, r37, r38, r39, r40 : std_logic_vector (19 downto 1); variable r41, r42, r43, r44, r45, r46, r47, r48, r49, r50 : std_logic_vector (19 downto 1); variable r51, r52, r53, r54, r55, r56, r57, r58, r59, r60 : std_logic_vector (19 downto 1); variable r61, r62, r63, r64, r65, r66, r67, r68, r69, r70 : std_logic_vector (19 downto 1); variable r71, r72, r73, r74, r75, r76, r77, r78, r79, r80 : std_logic_vector (19 downto 1); variable r81, r82, r83, r84, r85, r86, r87, r88, r89, r90 : std_logic_vector (19 downto 1); variable r91, r92, r93, r94, r95, r96, r97, r98, r99, r100 : std_logic_vector (19 downto 1); variable r101, r102, r103 : std_logic_vector (19 downto 1); begin s01 := Sq_in(24) and Sq_in(6); s02 := Sq_in(23) and Sq_in(7); s03 := Sq_in(22) and Sq_in(8); s04 := Sq_in(21) and Sq_in(9); s05 := Sq_in(20) and Sq_in(10); s06 := Sq_in(19) and Sq_in(11); s07 := Sq_in(18) and Sq_in(12); s08 := Sq_in(17) and Sq_in(13); s09 := Sq_in(16) and Sq_in(14); s10 := Sq_in(24) and Sq_in(7); s11 := Sq_in(23) and Sq_in(8); s12 := Sq_in(22) and Sq_in(9); s13 := Sq_in(21) and Sq_in(10); s14 := Sq_in(20) and Sq_in(11); s15 := Sq_in(19) and Sq_in(12); s16 := Sq_in(18) and Sq_in(13); s17 := Sq_in(17) and Sq_in(14); s18 := Sq_in(16) and Sq_in(15); s19 := Sq_in(24) and Sq_in(8); s20 := Sq_in(23) and Sq_in(9); s21 := Sq_in(22) and Sq_in(10); s22 := Sq_in(21) and Sq_in(11); s23 := Sq_in(20) and Sq_in(12); s24 := Sq_in(19) and Sq_in(13); s25 := Sq_in(18) and Sq_in(14); s26 := Sq_in(17) and Sq_in(15); s27 := Sq_in(24) and Sq_in(9); s28 := Sq_in(23) and Sq_in(10); s29 := Sq_in(22) and Sq_in(11); s30 := Sq_in(21) and Sq_in(12); s31 := Sq_in(20) and Sq_in(13); s32 := Sq_in(19) and Sq_in(14); s33 := Sq_in(18) and Sq_in(15); s34 := Sq_in(17) and Sq_in(16); s35 := Sq_in(24) and Sq_in(10); s36 := Sq_in(23) and Sq_in(11); s37 := Sq_in(22) and Sq_in(12); s38 := Sq_in(21) and Sq_in(13); s39 := Sq_in(20) and Sq_in(14); s40 := Sq_in(19) and Sq_in(15); s41 := Sq_in(18) and Sq_in(16); s42 := Sq_in(24) and Sq_in(11); s43 := Sq_in(23) and Sq_in(12); s44 := Sq_in(22) and Sq_in(13); s45 := Sq_in(21) and Sq_in(14); s46 := Sq_in(20) and Sq_in(15); s47 := Sq_in(19) and Sq_in(16); s48 := Sq_in(18) and Sq_in(17); s49 := Sq_in(24) and Sq_in(12); s50 := Sq_in(23) and Sq_in(13); s51 := Sq_in(22) and Sq_in(14); s52 := Sq_in(21) and Sq_in(15); s53 := Sq_in(20) and Sq_in(16); s54 := Sq_in(19) and Sq_in(17); s55 := Sq_in(24) and Sq_in(13); s56 := Sq_in(23) and Sq_in(14); s57 := Sq_in(22) and Sq_in(15); s58 := Sq_in(21) and Sq_in(16); s59 := Sq_in(20) and Sq_in(17); s60 := Sq_in(19) and Sq_in(18); s61 := Sq_in(24) and Sq_in(14); s62 := Sq_in(23) and Sq_in(15); s63 := Sq_in(22) and Sq_in(16); s64 := Sq_in(21) and Sq_in(17); s65 := Sq_in(20) and Sq_in(18); s66 := Sq_in(24) and Sq_in(15); s67 := Sq_in(23) and Sq_in(16); s68 := Sq_in(22) and Sq_in(17); s69 := Sq_in(21) and Sq_in(18); s70 := Sq_in(20) and Sq_in(19); s71 := Sq_in(24) and Sq_in(16); s72 := Sq_in(23) and Sq_in(17); s73 := Sq_in(22) and Sq_in(18); s74 := Sq_in(21) and Sq_in(19); s75 := Sq_in(24) and Sq_in(17); s76 := Sq_in(23) and Sq_in(18); s77 := Sq_in(22) and Sq_in(19); s78 := Sq_in(21) and Sq_in(20); s79 := Sq_in(24) and Sq_in(18); s80 := Sq_in(23) and Sq_in(19); s81 := Sq_in(22) and Sq_in(20); s82 := Sq_in(24) and Sq_in(19); s83 := Sq_in(23) and Sq_in(20); s84 := Sq_in(22) and Sq_in(21); s85 := Sq_in(24) and Sq_in(20); s86 := Sq_in(23) and Sq_in(21); s87 := Sq_in(24) and Sq_in(21); s88 := Sq_in(23) and Sq_in(22); s89 := Sq_in(24) and Sq_in(22); s90 := Sq_in(24) and Sq_in(23); r01 := "000000000000000000" & s01; r02 := "000000000000000000" & s02; r03 := "000000000000000000" & s03; r04 := "000000000000000000" & s04; r05 := "000000000000000000" & s05; r06 := "000000000000000000" & s06; r07 := "000000000000000000" & s07; r08 := "000000000000000000" & s08; r09 := "000000000000000000" & s09; r10 := "00000000000000000" & s10 & '0'; r11 := "00000000000000000" & s11 & '0'; r12 := "00000000000000000" & s12 & '0'; r13 := "00000000000000000" & s13 & '0'; r14 := "00000000000000000" & s14 & '0'; r15 := "00000000000000000" & s15 & '0'; r16 := "00000000000000000" & s16 & '0'; r17 := "00000000000000000" & s17 & '0'; r18 := "00000000000000000" & s18 & '0'; r19 := "00000000000000000" & Sq_in(16) & '0'; r20 := "00000000000000000" & Sq_in(21) & '0'; r21 := "0000000000000000" & s19 & "00"; r22 := "0000000000000000" & s20 & "00"; r23 := "0000000000000000" & s21 & "00"; r24 := "0000000000000000" & s22 & "00"; r25 := "0000000000000000" & s23 & "00"; r26 := "0000000000000000" & s24 & "00"; r27 := "0000000000000000" & s25 & "00"; r28 := "0000000000000000" & s26 & "00"; r29 := "000000000000000" & s27 & "000"; r30 := "000000000000000" & s28 & "000"; r31 := "000000000000000" & s29 & "000"; r32 := "000000000000000" & s30 & "000"; r33 := "000000000000000" & s31 & "000"; r34 := "000000000000000" & s32 & "000"; r35 := "000000000000000" & s33 & "000"; r36 := "000000000000000" & s34 & "000"; r37 := "000000000000000" & Sq_in(17) & "000"; r38 := "00000000000000" & s35 & "0000"; r39 := "00000000000000" & s36 & "0000"; r40 := "00000000000000" & s37 & "0000"; r41 := "00000000000000" & s38 & "0000"; r42 := "00000000000000" & s39 & "0000"; r43 := "00000000000000" & s40 & "0000"; r44 := "00000000000000" & s41 & "0000"; r45 := "00000000000000" & Sq_in(22) & "0000"; r46 := "0000000000000" & s42 & "00000"; r47 := "0000000000000" & s43 & "00000"; r48 := "0000000000000" & s44 & "00000"; r49 := "0000000000000" & s45 & "00000"; r50 := "0000000000000" & s46 & "00000"; r51 := "0000000000000" & s47 & "00000"; r52 := "0000000000000" & s48 & "00000"; r53 := "0000000000000" & Sq_in(18) & "00000"; r54 := "000000000000" & s49 & "000000"; r55 := "000000000000" & s50 & "000000"; r56 := "000000000000" & s51 & "000000"; r57 := "000000000000" & s52 & "000000"; r58 := "000000000000" & s53 & "000000"; r59 := "000000000000" & s54 & "000000"; r60 := "00000000000" & s55 & "0000000"; r61 := "00000000000" & s56 & "0000000"; r62 := "00000000000" & s57 & "0000000"; r63 := "00000000000" & s58 & "0000000"; r64 := "00000000000" & s59 & "0000000"; r65 := "00000000000" & s60 & "0000000"; r66 := "00000000000" & Sq_in(19) & "0000000"; r67 := "00000000000" & Sq_in(23) & "0000000"; r68 := "0000000000" & s61 & "00000000"; r69 := "0000000000" & s62 & "00000000"; r70 := "0000000000" & s63 & "00000000"; r71 := "0000000000" & s64 & "00000000"; r72 := "0000000000" & s65 & "00000000"; r73 := "000000000" & s66 & "000000000"; r74 := "000000000" & s67 & "000000000"; r75 := "000000000" & s68 & "000000000"; r76 := "000000000" & s69 & "000000000"; r77 := "000000000" & s70 & "000000000"; r78 := "000000000" & Sq_in(20) & "000000000"; r79 := "00000000" & s71 & "0000000000"; r80 := "00000000" & s72 & "0000000000"; r81 := "00000000" & s73 & "0000000000"; r82 := "00000000" & s74 & "0000000000"; r83 := "00000000" & Sq_in(24) & "0000000000"; r84 := "0000000" & s75 & "00000000000"; r85 := "0000000" & s76 & "00000000000"; r86 := "0000000" & s77 & "00000000000"; r87 := "0000000" & s78 & "00000000000"; r88 := "0000000" & Sq_in(21) & "00000000000"; r89 := "000000" & s79 & "000000000000"; r90 := "000000" & s80 & "000000000000"; r91 := "000000" & s81 & "000000000000"; r92 := "00000" & s82 & "0000000000000"; r93 := "00000" & s83 & "0000000000000"; r94 := "00000" & s84 & "0000000000000"; r95 := "00000" & Sq_in(22) & "0000000000000"; r96 := "0000" & s85 & "00000000000000"; r97 := "0000" & s86 & "00000000000000"; r98 := "000" & s87 & "000000000000000"; r99 := "000" & s88 & "000000000000000"; r100 := "000" & Sq_in(23) & "000000000000000"; r101 := "00" & s89 & "0000000000000000"; r102 := '0' & s90 & "00000000000000000"; r103 := '0' & Sq_in(24) & "00000000000000000"; r <= r01 + r02 + r03 + r04 + r05 + r06 + r07 + r08 + r09 + r10 + r11 + r12 + r13 + r14 + r15 + r16 + r17 + r18 + r19 + r20 + r21 + r22 + r23 + r24 + r25 + r26 + r27 + r28 + r29 + r30 + r31 + r32 + r33 + r34 + r35 + r36 + r37 + r38 + r39 + r40 + r41 + r42 + r43 + r44 + r45 + r46 + r47 + r48 + r49 + r50 + r51 + r52 + r53 + r54 + r55 + r56 + r57 + r58 + r59 + r60 + r61 + r62 + r63 + r64 + r65 + r66 + r67 + r68 + r69 + r70 + r71 + r72 + r73 + r74 + r75 + r76 + r77 + r78 + r79 + r80 + r81 + r82 + r83 + r84 + r85 + r86 + r87 + r88 + r89 + r90 + r91 + r92 + r93 + r94 + r95 + r96 + r97 + r98 + r99 + r100 + r101 + r102 + r103; end process Squre; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity Cube is port( Cu_in : in std_logic_vector(24 downto 13); t : out std_logic_vector(12 downto 0) ); end Cube; architecture rtl of Cube is begin Cube : process (Cu_in) variable c01, c02, c03, c04, c05, c06, c07, c08, c09, c10 : std_logic; variable c11, c12, c13, c14, c15, c16, c17, c18, c19, c20 : std_logic; variable c21, c22, c23, c24, c25, c26, c27, c28, c29, c30 : std_logic; variable c31, c32, c33, c34, c35, c36, c37, c38, c39, c40 : std_logic; variable c41, c42, c43, c44, c45, c46, c47, c48, c49, c50 : std_logic; variable c51, c52, c53, c54, c55, c56, c57, c58, c59, c60 : std_logic; variable c61, c62, c63, c64, c65, c66, c67, c68, c69, c70 : std_logic; variable c71, c72, c73, c74, c75, c76, c77, c78, c79 : std_logic; variable t01, t02, t03, t04, t05, t06, t07, t08, t09, t10 : std_logic_vector (11 downto 0); variable t11, t12, t13, t14, t15, t16, t17, t18, t19, t20 : std_logic_vector (11 downto 0); variable t21, t22, t23, t24, t25, t26, t27, t28, t29, t30 : std_logic_vector (11 downto 0); variable t31, t32, t33, t34, t35, t36, t37, t38, t39, t40 : std_logic_vector (11 downto 0); variable t41, t42, t43, t44, t45, t46, t47, t48, t49, t50 : std_logic_vector (11 downto 0); variable t51, t52, t53, t54, t55, t56, t57, t58, t59, t60 : std_logic_vector (11 downto 0); variable t61, t62, t63, t64, t65, t66, t67, t68, t69, t70 : std_logic_vector (11 downto 0); variable t71, t72, t73, t74, t75, t76, t77, t78, t79, t80 : std_logic_vector (11 downto 0); variable t81, t82 : std_logic_vector (12 downto 0); begin c01 := Cu_in(13) and Cu_in(24); c02 := Cu_in(15) and Cu_in(23); c03 := Cu_in(17) and Cu_in(22); c04 := Cu_in(19) and Cu_in(23); c05 := Cu_in(19) and Cu_in(21); c06 := Cu_in(20) and Cu_in(21); c07 := Cu_in(14) and Cu_in(24); c08 := Cu_in(16) and Cu_in(23); c09 := Cu_in(18) and Cu_in(22); c10 := Cu_in(19) and Cu_in(24); c11 := Cu_in(20) and Cu_in(22); c12 := Cu_in(20) and Cu_in(21); c13 := Cu_in(14) and Cu_in(23) and Cu_in(24); c14 := Cu_in(15) and Cu_in(22) and Cu_in(24); c15 := Cu_in(16) and Cu_in(21) and Cu_in(24); c16 := Cu_in(16) and Cu_in(22) and Cu_in(23); c17 := Cu_in(17) and Cu_in(20) and Cu_in(24); c18 := Cu_in(17) and Cu_in(21) and Cu_in(23); c19 := Cu_in(18) and Cu_in(19) and Cu_in(24); c20 := Cu_in(18) and Cu_in(20) and Cu_in(23); c21 := Cu_in(18) and Cu_in(21) and Cu_in(22); c22 := Cu_in(19) and Cu_in(20) and Cu_in(22); c23 := Cu_in(15) and Cu_in(24); c24 := Cu_in(17) and Cu_in(23); c25 := Cu_in(19) and Cu_in(22); c26 := Cu_in(20) and Cu_in(23); c27 := Cu_in(15) and Cu_in(23) and Cu_in(24); c28 := Cu_in(16) and Cu_in(22) and Cu_in(24); c29 := Cu_in(17) and Cu_in(21) and Cu_in(24); c30 := Cu_in(17) and Cu_in(22) and Cu_in(23); c31 := Cu_in(18) and Cu_in(20) and Cu_in(24); c32 := Cu_in(18) and Cu_in(21) and Cu_in(23); c33 := Cu_in(19) and Cu_in(20) and Cu_in(23); c34 := Cu_in(19) and Cu_in(21) and Cu_in(22); c35 := Cu_in(16) and Cu_in(24); c36 := Cu_in(18) and Cu_in(23); c37 := Cu_in(20) and Cu_in(24); c38 := Cu_in(20) and Cu_in(22); c39 := Cu_in(21) and Cu_in(22); c40 := Cu_in(16) and Cu_in(23) and Cu_in(24); c41 := Cu_in(17) and Cu_in(22) and Cu_in(24); c42 := Cu_in(18) and Cu_in(21) and Cu_in(24); c43 := Cu_in(18) and Cu_in(22) and Cu_in(23); c44 := Cu_in(19) and Cu_in(20) and Cu_in(24); c45 := Cu_in(19) and Cu_in(21) and Cu_in(23); c46 := Cu_in(20) and Cu_in(21) and Cu_in(22); c47 := Cu_in(17) and Cu_in(24); c48 := Cu_in(19) and Cu_in(23); c49 := Cu_in(21) and Cu_in(23); c50 := Cu_in(21) and Cu_in(22); c51 := Cu_in(17) and Cu_in(23) and Cu_in(24); c52 := Cu_in(18) and Cu_in(22) and Cu_in(24); c53 := Cu_in(19) and Cu_in(21) and Cu_in(24); c54 := Cu_in(19) and Cu_in(22) and Cu_in(23); c55 := Cu_in(20) and Cu_in(21) and Cu_in(23); c56 := Cu_in(18) and Cu_in(24); c57 := Cu_in(20) and Cu_in(23); c58 := Cu_in(21) and Cu_in(24); c59 := Cu_in(18) and Cu_in(23) and Cu_in(24); c60 := Cu_in(19) and Cu_in(22) and Cu_in(24); c61 := Cu_in(20) and Cu_in(21) and Cu_in(24); c62 := Cu_in(20) and Cu_in(22) and Cu_in(23); c63 := Cu_in(19) and Cu_in(24); c64 := Cu_in(21) and Cu_in(23); c65 := Cu_in(22) and Cu_in(23); c66 := Cu_in(19) and Cu_in(23) and Cu_in(24); c67 := Cu_in(20) and Cu_in(22) and Cu_in(24); c68 := Cu_in(21) and Cu_in(22) and Cu_in(23); c69 := Cu_in(20) and Cu_in(24); c70 := Cu_in(22) and Cu_in(24); c71 := Cu_in(22) and Cu_in(23); c72 := Cu_in(20) and Cu_in(23) and Cu_in(24); c73 := Cu_in(21) and Cu_in(22) and Cu_in(24); c74 := Cu_in(21) and Cu_in(24); c75 := Cu_in(21) and Cu_in(23) and Cu_in(24); c76 := Cu_in(22) and Cu_in(24); c77 := Cu_in(23) and Cu_in(24); c78 := Cu_in(22) and Cu_in(23) and Cu_in(24); c79 := Cu_in(23) and Cu_in(24); t01 := "00000000000" & c01; t02 := "00000000000" & c02; t03 := "00000000000" & c03; t04 := "00000000000" & c04; t05 := "00000000000" & c05; t06 := "00000000000" & c06; t07 := "0000000000" & c07 & '0'; t08 := "0000000000" & c08 & '0'; t09 := "0000000000" & c09 & '0'; t10 := "0000000000" & c10 & '0'; t11 := "0000000000" & c11 & '0'; t12 := "0000000000" & c12 & '0'; t13 := "0000000000" & c13 & '0'; t14 := "0000000000" & c14 & '0'; t15 := "0000000000" & c15 & '0'; t16 := "0000000000" & c16 & '0'; t17 := "0000000000" & c17 & '0'; t18 := "0000000000" & c18 & '0'; t19 := "0000000000" & c19 & '0'; t20 := "0000000000" & c20 & '0'; t21 := "0000000000" & c21 & '0'; t22 := "0000000000" & c22 & '0'; t23 := "000000000" & c23 & "00"; t24 := "000000000" & c24 & "00"; t25 := "000000000" & c25 & "00"; t26 := "000000000" & c26 & "00"; t27 := "000000000" & c27 & "00"; t28 := "000000000" & c28 & "00"; t29 := "000000000" & c29 & "00"; t30 := "000000000" & c30 & "00"; t31 := "000000000" & c31 & "00"; t32 := "000000000" & c32 & "00"; t33 := "000000000" & c33 & "00"; t34 := "000000000" & c34 & "00"; t35 := "00000000" & c35 & "000"; t36 := "00000000" & c36 & "000"; t37 := "00000000" & c37 & "000"; t38 := "00000000" & c38 & "000"; t39 := "00000000" & c39 & "000"; t40 := "00000000" & c40 & "000"; t41 := "00000000" & c41 & "000"; t42 := "00000000" & c42 & "000"; t43 := "00000000" & c43 & "000"; t44 := "00000000" & c44 & "000"; t45 := "00000000" & c45 & "000"; t46 := "00000000" & c46 & "000"; t47 := "0000000" & c47 & "0000"; t48 := "0000000" & c48 & "0000"; t49 := "0000000" & c49 & "0000"; t50 := "0000000" & c50 & "0000"; t51 := "0000000" & c51 & "0000"; t52 := "0000000" & c52 & "0000"; t53 := "0000000" & c53 & "0000"; t54 := "0000000" & c54 & "0000"; t55 := "0000000" & c55 & "0000"; t56 := "000000" & c56 & "00000"; t57 := "000000" & c57 & "00000"; t58 := "000000" & c58 & "00000"; t59 := "000000" & c59 & "00000"; t60 := "000000" & c60 & "00000"; t61 := "000000" & c61 & "00000"; t62 := "000000" & c62 & "00000"; t63 := "00000" & c63 & "000000"; t64 := "00000" & c64 & "000000"; t65 := "00000" & c65 & "000000"; t66 := "00000" & c66 & "000000"; t67 := "00000" & c67 & "000000"; t68 := "00000" & c68 & "000000"; t69 := "0000" & c69 & "0000000"; t70 := "0000" & c70 & "0000000"; t71 := "0000" & c71 & "0000000"; t72 := "0000" & c72 & "0000000"; t73 := "0000" & c73 & "0000000"; t74 := "000" & c74 & "00000000"; t75 := "000" & c75 & "00000000"; t76 := "00" & c76 & "000000000"; t77 := "00" & c77 & "000000000"; t78 := "00" & c78 & "000000000"; t79 := '0' & c79 & "0000000000"; t80 := t01 + t02 + t03 + t04 + t05 + t06 + t07 + t08 + t09 + t10 + t11 + t12 + t13 + t14 + t15 + t16 + t17 + t18 + t19 + t20 + t21 + t22 + t23 + t24 + t25 + t26 + t27 + t28 + t29 + t30 + t31 + t32 + t33 + t34 + t35 + t36 + t37 + t38 + t39 + t40 + t41 + t42 + t43 + t44 + t45 + t46 + t47 + t48 + t49 + t50 + t51 + t52 + t53 + t54 + t55 + t56 + t57 + t58 + t59 + t60 + t61 + t62 + t63 + t64 + t65 + t66 + t67 + t68 + t69 + t70 + t71 + t72 + t73 + t74 + t75 + t76 + t77 + t78 + t79; t81 := t80 & '0'; t82 := '0' & t80; t <= t81 + t82; end process Cube; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity Accumul is port( AddSub2Out_s5 : in std_logic_vector(33 downto 0); r : in std_logic_vector(19 DOWNTO 1); t : in std_logic_vector(12 DOWNTO 0); S : out std_logic_vector(25 downto 0) ); end Accumul; architecture rtl of Accumul is begin accumul : process (AddSub2Out_s5, r, t) variable x, SQx, Cux : std_logic_vector (25 downto 0); begin x := AddSub2Out_s5(25 downto 0); SQx := "000000" & r & AddSub2Out_s5(15); CUx := "0000000000000" & t; S <= x + SQx + CUx; end process accumul; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity EXCEPTION is port( OPCODE_s5 : in std_logic_vector(2 downto 0); oprG_stat_s5 : in std_logic_vector(3 downto 0); oprL_stat_s5 : in std_logic_vector(3 downto 0); exp_s5 : in std_logic_vector(8 downto 0); lzLSB_s5 : in std_logic; F2I_IX_s5 : in std_logic; Cout_AB_s5 : in std_logic; Cout_Bias_s5 : in std_logic; F2I_IV_s5 : in std_logic; signA_s5 : in std_logic; signB_s5 : in std_logic; fracG_MSB_s5 : in std_logic; fracL_MSB_s5 : in std_logic; fracZero_s5 : in std_logic; tmpIX_s5 : in std_logic; tmpIX_MD_s5 : in std_logic; tmpUD_s5 : in std_logic; forceInf_I : out std_logic; D0_flag : out std_logic; IX_flag : out std_logic; IV_flag : out std_logic; OV_flag : out std_logic; UD_flag : out std_logic; forceInf : out std_logic; forceNaN : out std_logic; forceUD : out std_logic; forceZero : out std_logic ); end EXCEPTION; architecture rtl of EXCEPTION is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin EXCEPTION : process (OPCODE_s5, oprG_stat_s5, oprL_stat_s5, exp_s5, lzLSB_s5, F2I_IX_s5, Cout_AB_s5, Cout_Bias_s5, F2I_IV_s5, signA_s5, signB_s5, fracG_MSB_s5, fracL_MSB_s5, fracZero_s5, tmpIX_s5, tmpIX_MD_s5, tmpUD_s5) variable OPCODE : std_logic_vector (2 downto 0); variable OPRG_STAT, OPRL_STAT : std_logic_vector (3 downto 0); variable EXP : std_logic_vector (8 downto 0); variable lzLSB, fracG_MSB, fracL_MSB : std_logic; variable fracZero, tmpIX, tmpIX_MD, tmpUD : std_logic; variable SignA, SignB, F2I_IX, F2I_IV, Cout_AB, Cout_Bias: std_logic; variable tmp_IV_flag : std_logic; variable tmp_OV_flag : std_logic; variable tmp_UD_flag : std_logic; variable tmp_forceNaN : std_logic; constant Norm : std_logic_vector (3 downto 0) := "0000"; constant Zero : std_logic_vector (3 downto 0) := "0001"; constant Inf : std_logic_vector (3 downto 0) := "0010"; constant NaN : std_logic_vector (3 downto 0) := "0100"; constant DeNorm : std_logic_vector (3 downto 0) := "1000"; begin OPCODE := OPCODE_s5; OPRG_STAT := oprG_stat_s5; OPRL_STAT := oprL_stat_s5; EXP := exp_s5; lzLSB := lzLSB_s5; fracG_MSB := fracG_MSB_s5; fracL_MSB := fracL_MSB_s5; fracZero := fracZero_s5; tmpIX := tmpIX_s5; tmpIX_MD := tmpIX_MD_s5; tmpUD := tmpUD_s5; SignA := signA_s5; SignB := signB_s5; F2I_IX := F2I_IX_s5; F2I_IV := F2I_IV_s5; Cout_AB := Cout_AB_s5; Cout_Bias := Cout_Bias_s5; tmp_forceNaN := '0'; tmp_OV_flag := '0'; tmp_IV_flag := '0'; tmp_UD_flag := '0'; if (OPCODE = OP_F2I) then if (F2I_IV = '1') and (SignA = '0') then forceInf_I <= '1'; else forceInf_I <= '0'; end if; else forceInf_I <= '0'; end if; case OPCODE_s5 is when OP_ABS | OP_NEG => D0_flag <= '0'; IX_flag <= '0'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; when OP_F2I => D0_flag <= '0'; IX_flag <= F2I_IX; IV_flag <= F2I_IV; OV_flag <= '0'; UD_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '0'; if (F2I_IV = '1') and (SignA = '1') then forceZero <= '1'; else forceZero <= '0'; end if; when OP_I2F => D0_flag <= '0'; IX_flag <= tmpIX; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '0'; forceZero <= fracZero; when OP_ADD | OP_SUB => D0_flag <= '0'; -- UD_Flag Generation if (fracZero = '1') then tmp_UD_flag := '0'; else if (OPRG_STAT=Zero and OPRL_STAT=Zero) then -- Zero + Zero, Zero - Zero tmp_UD_flag := '0'; else tmp_UD_flag := tmpUD; end if; end if; UD_flag <= tmp_UD_flag; -- OV_Flag Generation if (OPRG_STAT=Inf or OPRL_STAT=Inf) then -- either one is Inf tmp_OV_flag := '0'; else if (OPRG_STAT=NaN or OPRL_STAT=NaN) then -- either one is NaN tmp_OV_flag := '0'; else if (EXP = "011111111") then -- (exp = 254 & frac = 1x.xxxx & lz = 0) or OPRG_STAT = Inf -- ==> overflow -- because if frac = 1x.xxxx and lz = 0, -- exponent will be incremented by 1 -- otherwise, exponent will not be incremented -- fraction will be arranged by the result_formatter tmp_OV_flag := '1'; else tmp_OV_flag := '0'; end if; end if; end if; OV_flag <= tmp_OV_flag; -- IV_Flag Generation if (OPRG_STAT = Inf and OPRL_STAT = Inf and OPCODE = OP_ADD and SignA /= SignB) then -- Inf - Inf tmp_IV_flag := '1'; else if (OPRG_STAT = Inf and OPRL_STAT = Inf and OPCODE = OP_SUB and SignA = SignB) then -- Inf - Inf tmp_IV_flag := '1'; else if ((OPRG_STAT=NaN and fracG_MSB='0') or (OPRL_STAT=NaN and fracL_MSB='0')) then -- either one is sNaN tmp_IV_flag := '1'; else tmp_IV_flag := '0'; end if; end if; end if; -- forceNaN if (OPRG_STAT = Inf and OPRL_STAT = Inf and OPCODE = OP_ADD and SignA /= SignB) then -- Inf - Inf tmp_forceNaN := '1'; else if (OPRG_STAT = Inf and OPRL_STAT = Inf and OPCODE = OP_SUB and SignA = SignB) then -- Inf - Inf tmp_forceNaN := '1'; else if (OPRG_STAT=NaN or OPRL_STAT=NaN) then -- either one is NaN tmp_forceNaN := '1'; else tmp_forceNaN := '0'; end if; end if; end if; IV_flag <= tmp_IV_flag; forceNaN <= tmp_forceNaN; -- IX_Flag Generartion IX_flag <= tmp_OV_flag; if (tmp_forceNaN = '1') then -- Inf - Inf, either one is sNaN IX_flag <= '0'; else if (tmp_OV_flag = '1') then IX_flag <= '1'; else if (OPRG_STAT=Norm and OPRL_STAT=Norm and tmp_UD_flag='1') then IX_flag <= '1'; else IX_flag <= tmpIX; end if; end if; end if; if (tmp_OV_flag = '1') then forceInf <= '1'; else if (tmp_IV_flag='0' and (OPRG_STAT=Inf or OPRL_STAT=Inf) and tmp_forceNaN='0') then forceInf <= '1'; else forceInf <= '0'; end if; end if; if (tmp_UD_flag = '1') then forceUD <= '1'; else forceUD <= '0'; end if; if (fracZero='1' and tmp_IV_flag='0' and OPRG_STAT/=Zero) then forceZero <= '1'; else forceZero <= '0'; end if; when OP_MUL => if ((OPRG_STAT=Inf and OPRL_STAT=Zero) or (OPRL_STAT=Inf and OPRG_STAT=Zero)) then -- Inf X Zero = qNaN, Invalid IV_flag <= '1'; tmp_OV_flag := '0'; tmp_UD_flag := '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '1'; forceUD <= '0'; forceZero <= '0'; else if (OPRG_STAT=NaN and fracG_MSB='0') or (OPRL_STAT=NaN and fracL_MSB='0') then -- sNaN X .... = qNaN, Invalid IV_flag <= '1'; tmp_OV_flag := '0'; tmp_UD_flag := '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '1'; forceUD <= '0'; forceZero <= '0'; else if (OPRG_STAT=NaN or OPRL_STAT=NaN) then -- qNaN X .... = qNaN IV_flag <= '0'; tmp_OV_flag := '0'; tmp_UD_flag := '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '1'; forceUD <= '0'; forceZero <= '0'; else if (OPRG_STAT=Inf or OPRL_STAT=Inf) then -- Inf X .... = Inf IV_flag <= '0'; tmp_OV_flag := '0'; tmp_UD_flag := '0'; D0_flag <= '0'; forceInf <= '1'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; else if (OPRG_STAT=Zero or OPRL_STAT=Zero) then -- Zero X .... = Zero IV_flag <= '0'; tmp_OV_flag := '0'; tmp_UD_flag := '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '1'; else if ((EXP(8) = '1') and (Cout_Bias = '1')) then -- EXP[7:0] == 8'b11111111) // Overflow IV_flag <= '0'; tmp_OV_flag := '1'; tmp_UD_flag := '0'; D0_flag <= '0'; forceInf <= '1'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; else if ((EXP(8) = '1') and (Cout_Bias = '0')) then -- EXP[7:0] == 8'b00000000) // Underflow or DeNorm if (EXP < "111101001") then -- Underflow IV_flag <= '0'; tmp_OV_flag := '0'; tmp_UD_flag := '1'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '1'; else -- DeNorm IV_flag <= '0'; tmp_OV_flag := '0'; tmp_UD_flag := '1'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '1'; forceZero <= '0'; end if; else if (EXP = "11111111") then -- Overflow IV_flag <= '0'; tmp_OV_flag := '1'; tmp_UD_flag := '0'; D0_flag <= '0'; forceInf <= '1'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; else if (EXP = "00000000") then -- EXP = 0 IV_flag <= '0'; tmp_OV_flag := '0'; tmp_UD_flag := '1'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '1'; forceZero <= '0'; else -- Normal Case IV_flag <= '0'; tmp_OV_flag := '0'; tmp_UD_flag := '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; end if; end if; end if; end if; end if; end if; end if; end if; end if; if (OPRG_STAT=NaN or OPRL_STAT=NaN) then IX_flag <= '0'; else if tmp_OV_flag = '1' then IX_flag <= '1'; else IX_flag <= tmpIX_MD or tmp_UD_flag; end if; end if; OV_flag <= tmp_OV_flag; UD_flag <= tmp_Ud_flag; when OP_DIV => case OPRL_STAT is when NaN => -- xxx / qNaN = qNaN, xxx / sNaN = qNaN, Invalid IX_flag <= '0'; IV_flag <= not (fracL_MSB); OV_flag <= '0'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '1'; forceUD <= '0'; forceZero <= '0'; when Zero => if (OPRG_STAT = Zero) then -- 0 / 0 = qNaN, Invalid IX_flag <= '0'; IV_flag <= '1'; OV_flag <= '0'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '1'; forceUD <= '0'; forceZero <= '0'; else if (OPRG_STAT = Inf) then -- Inf / 0 = Inf IX_flag <= '0'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '1'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; else if (OPRG_STAT = NaN) then -- NaN / 0 = qNaN IX_flag <= '0'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '1'; forceUD <= '0'; forceZero <= '0'; else -- xxx / 0 = Inf, DivBy0 IX_flag <= '0'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '0'; D0_flag <= '1'; forceInf <= '1'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; end if; end if; end if; when Inf => if (OPRG_STAT = Inf) then -- Inf / Inf = qNaN, Invalid IX_flag <= '0'; IV_flag <= '1'; OV_flag <= '0'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '1'; forceUD <= '0'; forceZero <= '0'; else -- xxx / Inf = 0 IX_flag <= '0'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '1'; end if; when others => if (OPRG_STAT = Inf) then -- Inf / xxx = Inf IX_flag <= '0'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '1'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; else if (OPRG_STAT = Zero) then -- 0 / xxx = 0 IX_flag <= '0'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '1'; else if ((EXP(8) = '1') and ((Cout_AB = '1')or(Cout_Bias = '1'))) then -- EXP[7:0] == 8'b11111111) -- Overflow -> Result = Inf, OV, Inexact IX_flag <= '1'; IV_flag <= '0'; OV_flag <= '1'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '1'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; else if ((EXP(8) = '1') and ((Cout_AB = '0')and(Cout_Bias = '0'))) then -- EXP[7:0] == 8'b00000000) -- Underflow or DeNorm if (EXP < "111101001") then -- Underflow IX_flag <= '1'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '1'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '1'; else -- DeNorm IX_flag <= '1'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '1'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '1'; forceZero <= '0'; end if; else if (EXP = "11111111") then -- Overflow IX_flag <= '1'; IV_flag <= '0'; OV_flag <= '1'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '1'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; else if (EXP = "00000000") then -- EXP = 0 IX_flag <= '1'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '1'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '1'; forceZero <= '0'; else -- Normal Case IX_flag <= '0'; IV_flag <= '0'; OV_flag <= '0'; UD_flag <= '0'; D0_flag <= '0'; forceInf <= '0'; forceNaN <= '0'; forceUD <= '0'; forceZero <= '0'; end if; end if; end if; end if; end if; end if; end case; -- case(OPRL_STAT) if (((OPRG_STAT=NaN) and (fracG_MSB='0')) or ((OPRL_STAT=NaN) and (fracL_MSB='0'))) then --either of them is sNaN IV_flag <= '1'; IX_flag <= '0'; OV_flag <= '0'; forceNaN <= '1'; else if ((OPRG_STAT=NaN) or (OPRL_STAT=NaN)) then -- either of them is qNaN IX_flag <= '0'; OV_flag <= '0'; forceNaN <= '1'; -- result = qNaN end if; end if; when others => null; end case; -- case(OPCODE) end process EXCEPTION; end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; entity ResFormat is port( OPCODE_s5 : in std_logic_vector(2 downto 0); sign_s5 : in std_logic; exp_s5 : in std_logic_vector(8 downto 0); FRAC : in std_logic_vector(31 downto 0); forceNaN : in std_logic; forceInf : in std_logic; forceUD : in std_logic; forceZero : in std_logic; forceInf_I : in std_logic; Result : out std_logic_vector(31 downto 0) ); end ResFormat; architecture rtl of ResFormat is constant OP_ADD : std_logic_vector (2 downto 0) := "000"; constant OP_SUB : std_logic_vector (2 downto 0) := "001"; constant OP_F2I : std_logic_vector (2 downto 0) := "010"; constant OP_I2F : std_logic_vector (2 downto 0) := "011"; constant OP_NEG : std_logic_vector (2 downto 0) := "100"; constant OP_ABS : std_logic_vector (2 downto 0) := "101"; constant OP_MUL : std_logic_vector (2 downto 0) := "110"; constant OP_DIV : std_logic_vector (2 downto 0) := "111"; begin ResFormat : process (OPCODE_s5, sign_s5, exp_s5, FRAC, forceNaN, forceInf, forceUD, forceZero, forceInf_I) begin case OPCODE_s5 is when OP_NEG | OP_ABS => Result(31) <= sign_s5; Result(30 downto 23) <= exp_s5(7 downto 0); Result(22 downto 0) <= FRAC(29 downto 7); when OP_F2I => Result(31) <= sign_s5; if (forceInf_I = '1') then Result(30 downto 0) <= "111" & x"fffffff"; else if (forceZero = '1') then Result(30 downto 0) <= "000" & x"0000000"; else if (or_reduce(FRAC(30 downto 0)) = '0') then -- integer has only pZero Result(31 downto 0) <= x"00000000"; else Result(30 downto 0) <= FRAC(30 downto 0); end if; end if; end if; when others => -- OP_ADD, OP_SUB, OP_I2F, OP_MUL, OP_DIV Result(31) <= sign_s5; if (forceNaN = '1') then Result(31 downto 0) <= x"7fff0000"; else if (forceInf = '1') then Result(30 downto 0) <= "111" & x"f800000"; else if (forceUD = '1') then Result(30 downto 0) <= "000" & x"0800000"; else if (forceZero = '1') then Result(30 downto 0) <= "000" & x"0000000"; else Result(30 downto 23) <= exp_s5(7 downto 0); if FRAC(31) = '1' then Result(22 downto 0) <= FRAC(30 downto 8); else Result(22 downto 0) <= FRAC(29 downto 7); end if; end if; end if; end if; end if; end case; end process ResFormat; end rtl;