/********************************************/ /* Mode Definition File for Delay Test */ /* on Combinational Circuit (no scan) */ /* */ /* by Ekarat Laohavaleeson */ /* last modified: 01/31/2007 */ /********************************************/ TESTER_DESCRIPTION_RULE = dummy_tester ; SCAN TYPE = NONE //not scan design ; TEST_TYPES = DYNAMIC LOGIC SIG = NO //no signature analysis ; FAULTS = DYNAMIC, STATIC //fault model ; OPCG TYPE = NONE //no cut point so no OPCG logic ;