-
We need to treat the general case of a
k-output
circuit.
-
There are several possibilities:
-
Multiplex the
k
outputs of the CUT.
-
The multiplexer compacts the responses of each PO one at a time.
-
k
times slower but the 2
-N
aliasing probability is reduced when multiple POs are tested independently.
-
Bellmac uses both
parity
and
signature analysis
compaction.
-
For example, given the error responses:
|
Patterns
|
E1
|
E2
|
E3
|
E4
|
Parity
|
|
T1
|
1
|
0
|
0
|
0
|
1
|
|
T2
|
0
|
1
|
1
|
0
|
0
|
|
T3
|
0
|
1
|
0
|
1
|
0
|
|
T4
|
0
|
1
|
1
|
0
|
0
|
|
T5
|
1
|
1
|
1
|
0
|
1
|
-
The "parity" polynomial, X
4
+ 1, is then feed to the LFSR, which is divided by P(X) = X
4
+ X + 1.
-
This yields a remainder of R(X) = X.
-
Parallel Signature Analysis (Multiple Input Signature Register or
MISR
).
-
This scheme is equivalent
k
single input SAs but with the input stream
shifted in time
, M(X) = M
0
(X) + XM
1
(X) + ... + X
k
M
k
(X).
-
The
error polynomial
of the four outputs is E(X) = E
1
(X) + XE
2
(X) + X
2
E
3
(X) + X
3
E
4
(X), which is divided by the P(X) yeilding a remainder of X
3
+ X + 1.
-
Note that the aliasing probability of the MISR is still 2
-N
for an
N-stage
SA.
-
When the number of outputs,
k
, of the CUT is >
N
, parity/MUX can be used.
-
The effectiveness of any test can be measured by:
-
It's fault coverage
-
It's length
-
It's hardware requirements
-
It's data storage requirements
-
PR tests generated according to previous methods are usually long and result in unacceptable fault coverage:
-
Saturation
follows the rapid increase in fault coverage.
-
represents the
hard-to-detect
faults by random patterns (
RPR
).
-
The fault coverage can be improved by reducing the aliasing probability.
-
However, the main source of difficulty is that some faults are detected by
only a couple
, possibly one, patterns.
-
The root of the problem: Under PR pattern generation, all FFs have
equal probability
of generating a 1 or 0.
-
However, detection probabilities for faults in gates do not follow this distribution, e.g., only 1 pattern detects an
SA0
on an input to a
6-input
NOR.
-
Weighted PR TPG
assigns weights to the PIs, the probability that 1 should be assigned to a PI.
-
Weight assignment can be based on
circuit structure analysis
or
fault detection probabilities
.
-
Although coverage is improved, there are still
hard-to-detect
faults.
-
This results from fan-out, e.g., an input
common
to the AND and OR gate is assigned a weight that favors one over the other.
-
Multiple weights is a solution but adds hardware.
-
Other solutions: test point insertion, reseeding the LFSR and multiple polynomial LFSRs add hardware, impact performance and/or require long tests.
-
Mixed-mode approach uses
deterministic patterns
stored in ROM or via
bit-fixing
/
flipping
from LFSR patterns for RPR faults.
-
No good solutions, deterministic patterns are typically applied via scan path.
-
The LFSR and SA can be on-chip or off-chip, and as indicated, logic BIST typically combines PR testing with scan and boundry-scan.
-
Circular BIST
: For register-based architectures.
-
Three phases to the test:
Initialization
: all STSR and FFs.
Test mode
: all STSR act as LFSR and MISR.
Response Eval
: STSRs are compared with fault-free value.
-
BILBO
(Built-In Logic Blocks Observer): BIST + Scan Path.
-
Combines TPG and response compression in a single unit (designed for bus-oriented systems).
-
It uses existing FFs on-chip for PR TPG and SA.
-
C
1
and C
2
configure as a
shift register
for scan (00), an
LFSR
(00),
MISR
(10) a
Normal
(11).
-
Testing Combo-1 involves configuring BILBO as a
MISR
.
-
Afterwards, testing Combo-2 involves configuring BILBO as an
LFSR
.
-
Random Test Socket
: Combines scan and BIST.
-
All PIs are connected to the taps of LFSR #1 and all POs to the MISR.
-
FFs are scannable and form a Shift Register (SR).
-
SI is driven by LFSR #2 while SO is connected to the SSA.
-
Called "
test per scan
" instead of "
test per clk
" since shifting is necessary.
-
Note, LFSR 1 and 2 can be combined as well as the MISR and SSA.
-
Adv: low-cost ATPG, Disadv: overhead and long test times.
-
STUMPS
: Self-Test Using MISR and Parallel Shift reg. sequence generator.
-
Originally proposed to reduce overhead of LFSR/MISR for application to testing multi-chip boards, each of which has only the SRs.
-
Can also be used on a single chip with
multiple scan chains
.
-
Inputs to all scan chains provided by multiple-output LFSR.
