-
Originally a DFT technique for PCBs.
-
Boundry-Scan requires extra hardware in the ICs to facilitate communication with other ICs and the PCB.
-
The characteristics of SOC may be able to make use of these techniques.
-
In circuit
testing using a "bed of nails" fixture for PCBs (late '70s) has been replaced with Boundry-Scan due to:
-
Decrease in board size.
-
Increase in device density.
-
Change to surface mount technology.
-
A group of European electronics companies met in '85, called
Joint Test Action Group
(JTAG), and proposed a solution.
-
In '90, the methodology became IEEE/ANSI Standard 1149.1
-
Boundry-Scan has been extended to the chip level to run BIST.
-
PCB testing in the late '60s that took 3-4 minutes became 3-4 hours.
-
Board testing was originally performed using
functional testing
or
in-circuit
testing.
-
Functional testing
could be performed at speed but had several disadvantages:
-
It is not based on a fault model (no way to verify its quality).
-
Very limited diagnostic capabilities.
-
In-circuit
testing allowed testing of individual discrete or ICs on a fully assembled PCB.
-
Attributes include:
-
All PCB nodes must be accessible.
-
All components need to be isolated during testing from other components on the board.
-
Bed-of-nails was used up through the early '80s for in-circuit testing.
-
The "nails" are small
spring-loaded probes
that touched the solder pads on the bottom side of the UUT.
-
Problems with in-circuit testing:
-
Fixtures were custom made and could not be started until the design was complete.
-
This introduced delays and increased time-to-market.
-
The spring-loaded nails were easily damaged.
-
If the input to the CUT could not be easily derived from the driving chip, the tester had to force these values.
-
This caused
overheating
and required cooling periods, prolonging test.
-
Injected signals produced noise on the PCB, which caused incorrect CUT responses and latch-up.
-
These problems got worse as PCB traces got thinner.
-
Today, changes to IC surface mount packaging, decreases in pin pitch and IC mounting on both sides of the PCB challenge in-circuit testing.
-
Boundry-Scan provides the benefits of in-circuit testing but it reduces the number of "nails" required while maintaining fault coverage.
-
The required hardware components on the board and each IC for Boundry-Scan:
-
A Test Access Port (
TAP)
with 4 to 5 pins.
-
A set of registers: an instruction register (
IR
) and data registers (
DR
s).
-
A
TAP controller
(a 16-state FSM).
-
4 mandatory pins drive the TAP.
-
Two data pins (Test Data Input or
TDI
and Test Data Output
TDO
).
-
Two control pins (Test Mode Select or
TMS
and Test Clock
TCK
).
-
There are two manidatory data registers, a
bypass register
and a
Boundry-Scan Register
(
BSR
), which consists of Boundary-Scan cells (BSCs).
-
I/O signals of all chips enter and leave the chip through the
BSC
s.
-
Basically,
BSC
are scan FFs.
-
The TAP controller manages the exchange of data and instructions among the board and chips.
-
The BSCs can be configured to test the interconnect between chips (
External testing
) or the logic within the chip (
Internal testing
).
-
Test Access Port:
-
TRST
: used to reset the test logic asynchronously.
-
TDI
/
TDO
: scan-in and scan-out ports, serially connected.
-
TCK
: Synchronous test clock used for scanning and transferring data among the TAP registers.
-
TMS
: Test mode select, input to the TAP controller -- used to control its test operations.
-
The
Boundry-Scan Cell
(
BSC
)
-
BSC
are inserted at the I/O ports.
-
The I/O signal of the CUT goes through M
2
only (
Test/Normal
=0).
-
For test mode,
Shift/Load
=1, (To apply test,
UpdateDR
and
Test/Normal
=1).
-
Bypass Register
is actually a latch:
-
It is used to
bypass
shifting through the
BSC
in the CUT, to save test time.
-
For example, a
30
chip PCB, each having
100
BSC
s requires
3000
clocks.
-
If the
bypass
register is used, only a maximum of
129
clocks are necessary,
100
to shift data out of the CUT and
29
bypass shifts.
-
BSC
s are used to test interconnects/logic between Boundary-Scan IC on board, which can include non-Boundary-Scan ICs, ROMs and RAMs.
-
Also allows observation of core logic data without interference.
-
IR
is a serial-in, parallel-out register.
-
A
16-state
FSM that loads the
IR
, provides control for shifting data from
TDI
to
TDO
, performs test functions, such as capture, shift and update test data.
-
This FSM runs synchronously with
TCK
and responds to
TMS
signals.
-
Starting state at power-up is
Test-Logic-Reset
.
-
It stays here as long as
TMS
is high (CUT normal mode).
-
Note that it can be reached from any other state by holding
TMS
high and clocking at least 5 times.
-
With
TMS
at 0,
Run-Test-Idle
is active on the next
TCK
.
-
Here BIST may be initiated or the TAP idles between scan operations.
-
To start testing, the instruction needs to be loaded into
IR
.
-
TMS
held high and
TCK
clocked twice (
Select-IR-Scan
).
-
This connects
TDI
and
TDO
to
IR
.
-
With
TMS
at 0,
Capture-IR
state becomes active and then
Shift-IR
, which allows the instruction to be scanned in, to the
IR
.
-
Two clocks with
TMS
at 1 causes instruction transfer to output latches.
-
Read through the text for other details.
-
Normal operation
: Already discussed, Boundary-Scan is transparent.
-
External Testing
:
EXTEST
instruction loaded into
IR
.
-
Shift-DR
: Shift in the stimulus data via
TDI
.
-
Update-DR
: Apply scan data to output pins of Chip 1.
-
Capture-DR
: Latch results on input pins of Chip 2.
-
Shift-DR
: Shift out the results.
-
Testing Internal Logic
:
INTEST
instruction loaded into IR.
-
Same procedure except role reversal of inputs and outputs.
-
BIST Execution
:
RUNBIST
instruction used to trigger BIST test. When test completes, results are scanned out
TDO
for observation.
-
Cost
: Area overhead for small chips, 4 extra pins.
