ATPG Algorithms

ATPG Algorithms

Characteristics of the three main algorithms:
Roth's D-Algorithm (D-ALG) defined the calculus and algorithms for ATPG using D-cubes.
Goel's PODEM used path propagation constraints to limit the ATPG search space and introduced backtrace.
Fujiwara's FAN efficiently constrained the backtrace to speed up search and further limited the search space.

D-Calculus and D-Algorithm

Definitions:

Singular cover: Defined to be the minimal set of input signal assignments needed to represent essential prime implicants in Karnaugh map.

D-Calculus and D-Algorithm

D-cube: A collapsed truth table entry.

For example, combine rows 3 and 1 of the AND gate singular cover, and express it in Roth's 5-valued algebra (row 3 is good machine).

D 1 D

Rows 3 and 2 yield the propagation D-cube:

1 D D

A third is D D D.
Inverting D to D in each of these yields the 6 D-cubes for the AND gate.
3 of the NOR gate D-cubes are:

D 0 D
0 D D
D D D

D-intersection: Define how different D-cubes can coexist for different gates in a logic circuit.

D-Calculus and D-Algorithm

D-intersection (cont.):

For example, "0 X X" intersect "1 X X" is the empty cube (incompatible).

D-intersection	0	1	X	D	D
0	0	f	0	y	y
1	f	1	1	y	y
X	0	1	X	D	D
D	y	y	D	m	l
D	y	y	D	l	m

The greek symbols phi and psi represent incompatible assignments.

If the values are incompatible during propagation or implications, the assignment is called inconsistent and backtracking is necessary.

Greek symbols mu and lambda indicate incompatibilities if both are present in D-cubes with multiple input D and D.

For example, if only lambda occurs, invert the Ds in the second cube and perform intersection.

D-Calculus and D-Algorithm

D-contains: A cube A D-contains cube B if the set of A cube vertices contains (is a superset of) the B cube vertices.

Primitive D-cubes of failure (PDF): These model faults including:

(a) SA0 (represented by D)
(b) SA1 (represented by D)
(c) Bridging faults (short circuits)
(d) arbitrary change in logic gate function (e.g., from AND to OR).

For the AND gate, the PDF for output SA0 is "1 1 D"

Here the good machine generates a 1 when both inputs are 1, while the bad machine generates a 0.

The PDFs for the AND gate output SA1 are "0 X D" and "X 0 D".

Note the PDF are distinct from the propagation D-cubes.

The former models a failure at the gate.
The latter models the conditions for fault effect propagation.

D-Calculus and D-Algorithm

Implication procedure: Consists of the following steps:

(a) Model the fault with the appropriate PDF.
(b) Select propagation D-cubes to propagate fault-effect to PO(s)(D-drive).
(c) Select singular cover cubes to justify internal circuit signals (consistency procedure).

The D-algorithm's main problem is that it selects cubes and singular covers arbitrarily during test generation.

D-ALG

D-ALG Examples

D-ALG Examples

The following procedure is carried out for d SA0 in the previous circuit:

Step	A	B	C	d	e	F	Type of cube
1	1	1		D			PDF for AND gate
2				D	0	D	Propagation D-cube for NOR gate
3		1	1		0		Singular cover of NAND gate

Example #2:

D-ALG Examples

Steps followed to generate test cube (tc):

	Step		A	B	C	D	e	f	g	h	k	L
D-drive	1		D
	2		D					0		D
	3		D					0		D	1	D
Consistency	4	or							1		1
	5	not						0	1
	6	or			0		0	0
	7	and		0			0
		tc	D	0	0		0	0	1	D	1	D
D-chain dies

This example and table is given in Roth's paper.

Several other examples are covered in the paper.

Note that all implications are performed in the consistency procedure here.

A later example by our authors indicates the implications are carried out after each D propagation step in the D-drive?

D-ALG Examples

Example #3:

D-ALG Examples

Example #4:

D-ALG Examples

Example #5:

The B = 0 choice is eventually discovered as a bad choice.
One backtrack to step 2, which sets B = 1 and leads to the successful generation of a test.
Note here that implications carried out before the D-drive is completed.

PODEM

In late '70s, IBM introduced error correction and translation (ECAT) to their DRAM to increase reliability.

D-ALG failed to generate tests for these circuits because the search was not directed.

D-ALG will eventually determine that n = q is not realizable by this circuit.

PODEM

PODEM ( Path-Oriented Decision-Making) introduced several standard ATPG concepts:
PODEM expands the binary decision tree around the PIs and not around all circuit signals.

This reduces the size of the tree from 2n to 2num_PIs.

D-ALG tended to continue intersecting D-cubes even when the D-frontier disappeared.

PODEM introduced a subroutine to test if D-frontier still existed.

PODEM introduced objectives and realized that choosing PIs to set was important in efficiently realizing objectives.

Backtracing was used to obtain a PI assignment given an initial objective.

PODEM considered the length of the path between the objective and the POs and used controllability measures to guide the ATPG algorithm.

PODEM

PODEM starts at the PIs instead of at faulty line like D-ALG.

PODEM

PODEM finds a logic gate with D or D on its inputs that is closest to a PO.

The X-PATH-CHECK routine indicates that a path exists with unassigned signals from that gate to a PO then:
For propagating D, it would set the gate objective of obtaining a 1 on that gate output if it is an AND or OR or 0 if NAND or NOR.
For propagating D, the objective would be 0 for AND/OR and 1 for NAND/NOR.

Next, backtracing occurred from the objective to the PIs.

If all inputs had to be set, PODEM backtraced through the hardest-to-control input first.
If only one had to be set, it backtraced through the easier-to-control input.

This input became the next objective and the process is repeated.

PODEM

For example:

Select path s-Y (level distance 1 instead of path s-u-v-Z with 2).
X-PATH-CHECK determines that there is an X path along path s-Y.

Therefore, initial objective is to set r to 1.

PODEM

Since both input to XOR gate r need to be set, PODEM picks the hardest-to-control input n with objective of setting it to 0.

Backward implications: set m = 0 and set g = 0 leads to A = 0.
Forward implications: d = 0 and X = 1.

r is still not set.

Backward implications: set m = 0 and set k = 1 leads to B = 1.
Forward implications: k = 1, m = 0, r = 1, q = 1, Y = 1, s = D, u = D, v = D, Z = 1.

X-PATH-CHECK finds the D-frontier is empty, i.e., no X path from s to Y or Z.

Backtracking sets B = 0 and then A = 1, B = 0 (fault not sensitized).
Finally, A = 1, B = 1 results in success.

Note that the controllabilities did not help in this example but usually have a significant impact.

PODEM

Tree is searched depth-first.

Step	Action
1	Select path s-Y (initial objective r = 1)
2	Backtrace from r (stack implications A = 0)
3	Forward implic.: d = 0, X = 1
4	Backtrace from r again (stack implications A = 0, B = 1)
5	Forward implic.: k = 1, m = 0, r = 1, q = 1, Y = 1, s = D, u = D, v = D, Z = 1
6	X-PATH-CHECK shows paths are blocked, backtrack
7	Set B = 0
8	Forward implic.: d = 0, X = 1, m = 1, r = 0 (Fault not sensitized, bcktck).
9	Set A = 1 (backtrace from r).
10	Set B = 0
11	Forward implic.: d = 0, X = 1, m = 1, r = 0 (Fault not sensitized, bcktck).
12	Set B = 1 (implic.: d = 1, m = 1, r = 1, q = 0, s = D, v = D, X = 0, Y = D)

PODEM

For example:

Assigning A= 0 causes h= 0 , discard. Assign A= 1 .
Similarly, B= 0 is discarded and B= 1 selected.

Node n=0 becomes objective, leading to C=E= 0 => j= 0 and l= 1 .

Further resolution of n=0 leads to F=G= 0 => k= 0 , m= 1 , n= 0 and q= 1 , done!

FAN

Fujiwara and Shimono introduced several novel concepts to further limit the ATPG search space and accelerate backtracing:
Immediate Implications: PODEM misses opportunities to immediately assign value that are uniquely determined to signals.

Given objective L = 0, PODEM would backtrace and assign k=1, g=0 and B=0.
This is unfortunate since B=1 => h=1 and j=0 which prevents objective.

FAN

Unique Sensitization: There are other opportunities to find signals that are uniquely determined.

In this example, there is only one path over which the fault can propagate -- might as well set the off-path inputs immediately, i.e., c=1, G=1, A=1 and L=1.

FAN

Headlines: Defined as the "cut point" in a circuit that separates a cone of logic driven by PIs from the rest of the circuit.

Note that its always possible to justify a 0 or 1 from the headlines back to the PIs since there is no reconvergent fanout up to the headline.
This allows them to be removed from the decision tree and replaced with the headline.

FAN

Multiple Backtrace: FAN uses a breadth-first multiple backtrace procedure.

During backtrace, objectives are defined normally as a need for a 0 or a 1.

FAN defines an objective during a multiple-backtrace as a triple:

(s, n0(s), n1(s))
where s is the objective line, n0(s) is the # of times 0 is required at s and n1(s) is the # of times 1 is required at s.

FAN

For example, an objective to set line s to 0 is:

(s, n0(s), n1(s)) = (s, 1, 0)

and one to set line s to 1 is:

(s, n0(s), n1(s)) = (s, 0, 1)

Backward breadth-first processing of an AND gate yields, for example:

Here, the easiest-to-control input to set to 0 gets:

#0's = OUTPUT # 0's (OUTPUT # 1's)
#1's = OUTPUT # 1's (OUTPUT # 0's)

All other inputs:

#0's = 0 (0)
#1's = OUTPUT # 1's (OUTPUT # 0's)

FAN

For fanout stems:

For example:

Note that this indicates that it is possible to satisfy the initial objectives without requiring the off-path inputs y and z to be set.

FAN

In contrast:

Note that in this case, it is necessary to define the side inputs to establish the initial objectives.
Add y as an objective to satisfy in the breadth-first search.

Might as well assign some value (0) to the fanout stem since you need to force another implication (either y or m) in order to meet the initial objectives.

Advanced ATPG Algorithms

Dominator ATPG Programs: TOPS (Kirkland and Mercer)
Learning ATPG Programs:

SOCRATES (Schulz et al.)
EST (Giraldi and Bushnell)
Recursive Learning (Kunz and Pradhan)

Implication Graph ATPG Algorithms:

NNATPG (Chakradhar et al.)
TRAN (Chakradhar et al.)
GRASP
NEMESIS
TEGUS
A program by Tafertshofer et al.

BDD-Based ATPG Algorithms (performance poor on multipliers):

CATAPULT (Gaede at al.)
TSUNAMI (Stanion Bhattacharya)

Test Generation Systems

An ATPG system may contain:
Fault generator/collapsing program
RPG program
Fault simulator
ATPG program
Test compactor

Performance criteria include:
Fault coverage

Fault efficiency

Vector set size
CPU time

Test Generation Systems

SOCRATES: Starts with RPG (optionally with weighted pattern probabilities), concurrent fault simulation and fault dropping.

32 random patterns are generated in parallel and one concurrent fault simulation is carried out.

The process terminates when no faults are detected after 64 random patterns have been tried.

This is followed with several passes of ATPG.

Pass one is done usually with only 10 backtracks allowed per fault.
Each pattern is then fault simulated against all remaining faults and detected faults are dropped.
Later passes increase the number of backtracks to 50, 100 and finally 10,000.

This process outputs a test vector file, a list of undetected faults, a list of redundant faults, a list of aborted faults and a backtrack distribution file.

Test Compaction

Many ATPG systems use RPG to get 60% fault coverage, followed by ATPG.

However, many of the RPG patterns may not be as effective at providing "high" fault coverage.

At the end of ATPG, all patterns are fault simulated in reverse order of their generation.

Once fault coverage reaches 100%, the remaining RPG patterns are discarded.

This type of compaction greatly reduces the size of the test set.

An additional static compaction method is suitable for the ATPG generated patterns, where unassigned inputs are left at X.

Two patterns can be combined if they are compatible, as defined by the D-intersection operator given earlier.

Test Compaction

The degree of compaction possible depends on the order in which the vectors are processed.

Optimal static compaction algorithms are impractical, so heuristic algorithms are used.

Dynamic compaction immediately assigns 1's and 0's to the unassigned PIs after the ATPG program generates them.

The secondary faults detected allows additional fault dropping.

Extension of the vector is usually only done if the percentage of X's exceeds a user-specified percentage.