Economics Defined

Economics Defined

Engineers concerned with optimizing technological efficiency.

Economists prefer to minimize cost.

Fixed and variable costs of material, equipment, labor, etc. are important.

Test economics focuses on the relationship between testing cost and product quality.

The relationship is complex.
For complex systems, testing cost is > 30% of the total cost.

Testing is responsible for the quality of VLSI chips.

Goal: obtain required quality level at minimum cost.

Costs include:
Cost of ATE (initial and running).
Cost of test development (CAD tools, test generation, test programming).
Cost of DFT (scan reduces cost of test generation, BIST reduces complexity and cost of ATE).

Test Economics

Types of cost:
Fixed Cost (FC)

Things that are required, e.g., factory building.
The fixed cost per item reduces as production is increased.
E.g. purchase price of car: $25,000.

Variable Cost (VC)

This increases with production output, e.g. labor, energy and raw materials.
E.g. Gas, maintenance, etc.: 20 cents/mile.

Total Cost (TC)

Sum of fixed and variable -- increase with production.
E.g. $25,000 + 0.2m (for traveling m miles).

Average Cost (AC)

Total cost divided by the number of units produced.
E.g. $25,000/m + 0.2 (total cost/m).

Text gives examples and curves that illustrate tradeoffs.

Test Economics

Testing is difficult to justify if it delays introduction of the product.

There is an associated cost measured as the loss in market share due to the delay in reaching the market at the appropriate moment:

DFT and BIST can help avoid delays and reduce testing cost.

On the other hand, the cost of detecting a defect increases by an order of magnitude at every level of integration (power of ten rule).

Yield

Process yield: fraction of acceptable parts among all parts fabricated.

Wafer yield: average number of good chips/wafer.

Normalizing wafer yield by the # of chip sites on the wafer can be used as process yield.

Many factors affect yield including die area , process maturity and number of process steps .

It is difficult to obtain an exact value of yield:
Tests are based on fault models that do not detect all defective parts.
Lack of data once the product is sold.

Defect Level ( DL ) are the fraction of bad chips that pass final package tests.

DL is usually expressed in Defect-Per-Million or DPM .

Defect Modeling

Two scenarios for defect modeling:

Fortunately, clustered defect model better represents reality.

Random defects are characterized by two parameters:
defect density, d, which is the average number of defects per unit area.
clustering parameter, alpha.
The average number of defects on a chip of area A is Ad.

Defect Modeling

In any random chip, the number of defects, x, is an integer-valued random variable.

Defect clustering is best modeled assuming a negative binomial probability density function for x:

Yield Models

In order to predict the yield, we need the mean and variance for the number of defects on a chip.

Obtain either from experimental measurements or process simulation.

Substitution of the mean and variance in above equations gives yield parameters, d and alpha.

Yield is obtained as the probability, p(0), of no defect on a chip.

Substituting x=0 into the equation (1) gives:

For the unclustered model:

Yield Models

However, this model predicts low yields.

If Ad = 1.0 and alpha = 0.5 (typical of a large VLSI chip) then using (3):

Using (2), a more realistic prediction of 0.58 is obtained.

Yield may be low when fabricating a new design, and more accurately predicated by (3) than by (4).

For example: Calculate the cost of testability given the following:
d = 1.25 defects/cm2
alpha = 0.5
chip area, A, is 8mm X 8mm = 0.64cm2.
Equation (2) gives:

Example

Now suppose:
The process uses 8-inch wafers
The cost of processing a wafer is $100.
Each wafer has 400 chips.

Processing cost per chip is:

Assume the chip size increases by 10% after DFT is included. Yield is then:

With DFT, a wafer contains 400/1.1 ~= 364 chips. Therefore, processing cost is:

Yield and Defect Level

A second yield model: Murphy's model '64:

Relationships between Yield and Defect Level

Williams and Brown ('81):

For small values of DL , e.g., < 1000 DPM, McCluskey '89 gives it as:

Test Transparency ( TT ) is the fraction of defects that are NOT detected.

Yield and Defect Level

Often TT is approximated as 1 - C , where C is the SSA fault coverage.

In reality, TT >= 1 - C (more defects are missed than predicted).

The relationship between DL and T , plotted for yield= 50% and 90%:

H igh fault coverage is needed to get low defect levels , especially for low yield.

Yield and Defect Level

Experimental data indicates that Williams and Brown is pessimistic.

Maxwell '91:

For example, W&B indicates that 78% fault coverage is required to reach a DPM of 5.

Maxwell indicates that it is actually sufficient to reach only 50% fault coverage.

DL and Quality

DL (or reject ratio) is a measure of the effectiveness of the tests.

Objective is to develop a test that reduces the number of outgoing faulty parts to an acceptable level
It's too expensive to try to get them all.

The DL can be determined from the field return data.

Chips are returned if they fail acceptance test, fail system test or fail in the field during a maintenance test.

For commercial VLSI chips, a DL >500ppm is considered unacceptable.

DL is difficult to determine:
Some failed parts are not returned.
Some returned parts are damaged in handling.
It takes a long time (a year) to collect sufficient data.
The DL reduces over time.

Therefore, computed DL is usually overly pessimistic.

Test data analysis from manufacturing test data gives estimate.

Estimating Defect Level

The yield equation (1) can be modified to do this.
Fault density (as opposed to defect density) defined as f = average number of SA faults per unit chip area.
Fault clustering parameter, beta
Stuck-At fault coverage, T.

Here, we obtain the "measured" yield when a test with fault coverage T is applied.

Assume that tests with 100% fault coverage (T=1.0) remove all faulty chips:

Af (average number of faults) and beta are determined from test data.

Estimating Defect Level from SEMATECH data

This model can be evaluated on IBM's SEMATECH data.

CUT characteristics:
CUT is a bus interface controller ASIC containing 116,000 equivalent 2-input NAND gates.
CUT has 249 I/O and a 304-pin package.
Some portions of chip operate at 40MHz, others at 50MHz.
Full scan, with 5,280 scan latches.
3.3V power supply, 3 metal, 0.45um technology, 9.4mm x 8.8 mm die size.
Four types of tests applied, SA, functional, delay and IDDQ.

IBM's LSSD scan chain design allows a scan flush test.

With scan tests, total SA coverage was 99.79% for a total of 375,142 faults.
Advantest 3381 ATE used.
18,466 chips tested at 2.5MHz test clock.

(Data provided courtesy Phil Nigh, IBM).

Estimating Defect Level from SEMATECH data

Fault coverage computed using a fault simulator:

Chip fallout vs. test vector number:

Estimating Defect Level from SEMATECH data

Sample of tabulated data from these two graphs:

Vector Number	Measured Incremental data		Normalized Incremental data
Vector Number	Faults detected	Chip fallout	Fault coverage	Chip fallout
1	26,587	1,673	0.071	0.0906
2	1,505	497	0.075	0.1175
3	2,923	5	0.083	0.1178
4	4.545	3	0.095	0.1180
5	21,841	2	0.153	0.1181
6	12,257	367	0.186	0.1379
7	959	159	0.188	0.1465
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
6,831	1	0	0.998	0.2386

Remember, total number of faults is 375,142 and 18,466 chips tested.

The key question is how many bad chips did not fallout after the testing stops?

Estimating Defect Level from SEMATECH data

The data from the last two columns can be plotted and fitted.

Plotted fallout rate function, 1 - Y(T), given by:

Fitting yields Af=2.1 and beta=0.083.
This gives f = Af/A = 2.1/(0.94*0.88) = 2.54 faults/sq. cm.

Using these values, Eq (5) gives Y = 76.23 and (6) gives DL = 168 for T=0.9979

Estimating Defect Level from SEMATECH data

This type of analysis allows the yield and fault distribution parameters to be determined.

The fab process must be diagnosed and corrected if they are not as expected.

Also, if the defect level is too high, the fault coverage of the patterns must be improved.

Bear in mind, the tests in this study were run at slow speed.

Therefore, some chips that passed have delay faults.
Other tests may be necessary to make other defects have a non-zero probability of detection.

Deriving better tests is the focus of some recent research.

Eq (6) can be used to plot DL as a function of fault coverage.

Estimating Defect Level from SEMATECH data

Note, a reverse logarithmic scale is used for the x-axis.

For zero fault coverage, the DL is 237,700 ppm.

Therefore, the lot of chips contains 76.23% good chips.

For fault coverage at 99%, DL reduces to <1000 ppm.

For 99.9% -> <100 ppm, for 99.99 -> <10ppm.

Remember, these DLs are realistic only if testing emulates real conditions.

Another view: these are the DL if the chips are used at 2.5MHz.

Yield and Testing

Testing cannot improve process yield.

It is only a screening process for bad chips.

Process yield can be improved by:
Diagnosis and Repair

Parts that fail Go/No-Go can be diagnosed and repaired in some situations.
This strategy improves yield but also increases production cost.

Process Diagnosis and Correction

Failure analysis determines the root cause and the process is "corrected".
Therefore, this strategy is more cost effective.