-
Transistor level circuit representation is needed to understand how MOS circuits can fail.
-
Here, we can model the MOS transistor as an ideal switch.
-
Defects cause the switch to remain permanently open or closed.
-
Under this model, the I/O behavior of a faulty MOS circuit cannot be exactly represented by the SA fault model.
-
Stuck-Open Faults (SOP)
-
Defect creates an unintended high-impedance state on the output node of a gate.
-
The SOP model adds faults to the standard list of Stuck-At
faults.
-
Consider a 2-input NOR gate:
-
Stuck-At faults include: A-SA0
,
B-SA0
,
Out-SA0
and
Out-SA1
.
-
SOP
model adds three non-classical faults:
-
A-Stuck-Open
(
A-SOP
),
-
B-Stuck-Open
(
B-SOP
)
-
Vdd-Stuck-Open
(
VDD-SOP).
-
Exhaustive test AB = (00, 01, 10, 11) does not detect all faults.
-
For SOP, vector order is important.
-
For example, the sequence AB = (00, 01, 00, 10) is able to detect all faults on the NOR gate, including the SOP faults.
-
This test sequence tests each path between the output and VDD and GND independently.
-
The tests are really test sequences.
-
First pattern initializes the output node, second pattern checks for the presence of the fault.
-
Difficulties:
-
Delays to the inputs of the gates may be different creating intermediate states that invalidate the initializing test pattern.
-
Two-vector sequence TPG time for SOP faults is significantly longer than single-vector TPG time for SSF faults.
-
Switch-level test generation algorithms can automate the generation of these tests.
-
A gate level model is also possible:
-
Series connections of transistors are replaced with AND, parallel connections are replaced with OR.
-
pMOS inputs are inverted.
-
When the 2 inputs to BUS are different, output determined by C1.
-
In fault free circuit, this must be true since complementary logic functions drive BUS.
-
Complement of the
Stuck-Open
fault model is the
Stuck-On
fault model.
-
Stuck-On
faulty gate output is difficult to predict.
-
A transistor that is permanently stuck-on will, for some input combination(s), compete with its complementary transistors for control of the output.
-
Sometimes this competition does not result in a catastrophic failure.
-
Stuck-short faults modeled as SA0 on pMOS in gate-level equivalent model.
-
Modeled at the gate or transistor level as a short between 2 (simple) or more of signal lines.
-
Non-feedback versus feedback (memory) versions.
-
Fault is usually modeled using
wired logic
: AND and OR.
-
For CMOS, it
depends
on the
type of gates
driving the shorted lines and their
input values
.
-
The transistor
resistances
determine the appropriate model:
|
Input values
|
Resistance relationships
|
Resulting output value
|
Wired logic model.
|
|
A=B
|
Any ratio
|
C = D
|
AND, OR
|
|
A=0, B=1
|
RAp > RBn
|
C = D = 0
|
AND
|
|
RAp < RBn
|
C = D = 1
|
OR
|
|
A=0, B=1
|
RAn > RBp
|
C = D = 1
|
OR
|
|
RAn < RBp
|
C = D = 0
|
AND
|
-
Bridging faults that can not be represented by a
known
fault model.
-
Some convert
combination
circuits to
sequential
(feedback bridging).
-
Circuits with memory elements (FFs) need to be initialized.
-
Faults that interfere with this process are initialization faults.
-
The initial state of the FF is unknown after power-up.
-
To initialize Q to 0, set A = 1 & B = 0 and apply Clk.
-
With the SA0 fault, the FF remains in the unknown state.
-
A fault that does not modify the input-output function of the circuit.
-
They can be removed from the circuit.
-
A redundant fault cannot be detected using SSF tests.
-
For combinational circuits, identifying redundant faults is used in circuit optimizations.
-
For sequential circuits, it's more difficult to identify and remove redundancy.
-
In general, faults in sequential circuits for which no test can be found are called untestable faults.
-
Redundant faults are a subset of these.
-
The simultaneous presence of single faults, usually of the same type.
-
Usually not considered in practice:
-
We indicated earlier that there are 3n-1 possible multiple stuck-fault (MSF) in a circuit with n SSF sites.
-
Tests for SSFs cover a high percentage of MSFs.
-
Situations in which it is important to consider them:
-
Diagnostic or fault location procedures don't work with multiple faults.
-
A circuit with redundant single SSF can malfunction even when it passes the SSF tests.
-
Solution is to enhance test set to cover multiple faults or remove redundancy.
-
The latter is usually easier.
-
The three faults, SA1-3, are redundant because the presence of any one of them has no effect on the logic function.
-
As we will see, the vectors 00, 01, and 10 detect all other single SA faults.
-
However, in combination they can cause a problem.
-
For input combination 11, the function is incorrect, but its not part of the test set.
-
Intuitively, it seems that detecting all SSFs is sufficient to detect the MSFs.
-
Unfortunately, functional masking introduced by MSFs can prevent detection of SSFs.
-
Functional masking implies masking under any test set.
-
However, it's possible that a multiple fault is masked under a given test and not under another.
-
The test abc = 010 detects the MSF {c SA0, a SA1}.
-
Given a complete test set T for SSFs, can there exist a MSF F = {f1, f2, ..., fk} such that F is not detected by T?
-
Unfortunately, the answer is yes.
-
The test set T = {1111, 0111, 1110, 1001, 1010, 0101} detects all SSFs.
-
The only test in T that detects both f = b SA1 and g = c SA1 is 1001.
-
However, the circular masking of f and g under T prevents the MSF {f, g} from being detected.
-
Fortunately, circular masking relations are seldom encountered in practice.
-
Transition Fault (gross-delay faults):
-
Gate delay increased to point where transition does not reach output before end of clock period, even along the shortest path.
-
Gate-delay Fault:
-
Defect increases input to output delay of a single logic gate.
-
Line-delay Fault:
-
In contrast to transition fault, a test here must propagate the transition through the longest sensitizable path.
-
Path-delay Fault:
-
This fault causes the cummulative propagation delay of a path to increase beyond some specified time duration.
-
Segment-delay Faults:
-
A segment (of length L gates) delay fault increases the delay of a segment such that all paths containing the segment have a path-delay fault.
-
Segment-delay = Path-delay if L is the maximum combinational depth of the circuit.
-
Segment-delay = Transition fault if L is 1.
-
A fault for which no test can be found.
-
Two classes:
-
Faults that are redundant, i.e., their presence does not change the I/O function.
-
Faults that change the I/O function but no test can be found.
-
Initialization faults of sequential circuits belong to this class.
